# US 6,720,596 B2 · Semiconductor device and method for driving the same

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- Number: US 6,720,596 B2
- Document ID: US6720596B2
- Status: Granted
- Kind: B2
- Application number: 09/977,310
- Filed: 2001-10-16
- Published: 2002-04-18
- Granted: 2004-04-13
- Earliest claimed: 2000-10-17
- Assignees: Matsushita Electric Industrial Co., Ltd.
- Inventors: Takashi Ohtsuka; Kiyoyuki Morita; Michihito Ueda
- Web page: https://patentgrep.com/patent/US6720596B2

## CPC

- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- G11C 11/22: using ferroelectric elements
- H10B 53/30: characterised by the memory core region
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.

## Claims

### Claim 1

A nonvolatile memory, comprising:
a transistor having a source region, a drain region and a floating gate electrode; a dielectric capacitor, which is connected to the floating gate electrode and has a dielectric layer;
a ferroelectric capacitor, which is connected to the floating gate electrode and has a ferroelectric layer;
first and second polarization voltage application terminals, which are connected to the dielectric capacitor and the ferroelectric capacitor, respectively, and which apply voltage for generating polarization to the ferroelectric capacitor; and
a ground terminal and a power source voltage terminal connected to the source region and the drain region, respectively,
wherein the ground terminal and the power source voltage terminal are independent from the first and second polarization voltage application terminals.

### Claim 2 (depends on 1)

The nonvolatile memory according to claim 1, further comprising a pass transistor that is connected to either the source region or the drain region and carries out ON/OFF control with a control signal.

### Claim 3 (depends on 1)

The nonvolatile memory according to claim 1, further comprising second conductivity-type source and drain regions, which are provided within the semiconductor substrate at both sides of the floating gate electrode, and which are separated from the first conductivity-type source and drain regions;
wherein two MISFETs of opposite conductivity type are configured with the regions between the two source and drain regions serving as channel regions; and wherein the semiconductor device functions as a nonvolatile inverter.

### Claim 4 (depends on 3)

The nonvolatile memory according to claim 3, further comprising a first-stage inverter for inputting complementary signals to the ferroelectric capacitor and the dielectric capacitor;
wherein the semiconductor device functions as a nonvolatile flip-flop.

### Claim 5 (depends on 4)

The nonvolatile memory according to claim 4, further comprising an intermediate inverter, which is disposed between the first-stage inverter and either the ferroelectric capacitor or the dielectric capacitor.