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US 6,720,594 B2Granted
Image sensor array with reduced pixel crosstalk
AssigneeXerox Corporation
InventorsJeffrey T. Rahn, Koenraad F. Van Schuylenbergh, Jeng Ping Lu
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Abstract
Improved pixel circuits are disclosed for high fill-factor large area imager systems using continuous (e.g., amorphous silicon) sensor layers. A first approach prevents crosstalk by ensuring that each pixel is not able to go into saturation. A second approach employs a cascode transistor to maintain the bias of the sensor contact at a constant potential regardless of illumination condition. These two approaches may be combined. A resistive film connecting the pixel contacts may be used in conjunction with the second approach to prevent aliasing of signal and noise.
Claims26
An imager system comprising
- a scanning control circuit for generating gate voltage signals on a plurality of gate lines;
- a continuous sensor layer;
- a bias voltage source;
- and
- a plurality of pixels arranged in an array, each pixel including:
- a sensor including an associated portion of the continuous sensor layer and having a first terminal connected to the bias voltage source, the sensor also having a second terminal;
- a storage capacitor having a first terminal coupled to the second terminal of the sensor, and a second terminal connected to a system voltage source;
- and
- an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit;
- wherein the imager system further comprises means connected to at least one of the sensor and the access transistor of each of said plurality of pixels for controlling a voltage across the sensor of each of the plurality of pixels such that the sensor of each of the plurality of pixels is prevented from reaching saturation.
7 more elements
An imager system comprising;
- a scanning control circuit for generating gate voltage signals on a plurality of gate lines;
- a continuous sensor layer;
- a bias voltage source;
- and
- a plurality of pixels arranged in an array, each pixel including:
- a sensor including an associated portion of the continuous sensor layer and having a first terminal connected to the bias voltage source, the sensor also having a second terminal;
- a storage capacitor having a first terminal coupled to the second terminal of the sensor, and a second terminal connected to a system voltage Source;
- an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit;
- and
- a clamp transistor connected across the storage capacitor between the system voltage source and the second terminal of the sensor.
7 more elements
An imager System comprising:
- a scanning control circuit for generating gate voltage signals on a plurality of gate lines;
- a continuous sensor layer;
- a bias voltage source;
- and
- a plurality of pixels arranged in an array, each pixel including:
- a sensor having an first terminal connected to a bias voltage source, the sensor also having a second terminal;
- a storage capacitor including an associated portion of the continuous sensor layer and having a first terminal coupled to the second terminal of the sensor and a second terminal connected to a system voltage source;
- an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit;
- and
- a cascode transistor connected between the first terminal of the storage capacitor and the second terminal of the sensor.
7 more elements
An imager system comprising:
- a scanning control circuit for generating gate voltage signals on a plurality of gate lines;
- a continuous layer of sensor material including a plurality of spaced-apart, relatively highly doped regions, a continuous undoped layer formed over the plurality of relatively highly doped regions, and a continuous doped layer formed over the undoped layer;
- a bias voltage source;
- and
- a plurality of pixels arranged in an array, each pixel including:
- a sensor including an associated portion of the continuous layer of sensor material sensor and having a first terminal connected to a bias voltage source, the sensor also having a pixel contact abutting an associated highly doped region of the plurality of spaced apart highly doped regions;
- a storage capacitor having a first terminal and a second terminal, the second terminal being connected to a system voltage source;
- an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit;
- and
- a cascode transistor connected between the first terminal of the storage capacitor and the second terminal of the sensor,
- wherein the continuous layer further comprises a resistor region formed below the continuous undoped layer and contacting the plurality of spaced-apart, relatively highly doped regions, and
- wherein the resistor region has a doping level greater than the continuous undoped layer and less than the plurality of spaced-apart, relatively highly doped regions.
9 more elements
Dependencies are inferred from the claim text.