# US 6,720,591 B2 · Semiconductor integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,720,591 B2 - Document ID: US6720591B2 - Status: Granted - Kind: B2 - Application number: 10/127,583 - Filed: 2002-04-23 - Published: 2002-10-24 - Granted: 2004-04-13 - Earliest claimed: 2001-04-23 - Assignees: Renesas Technology Corp. - Inventors: Toshio Miyamoto; Ichiro Anjo; Asao Nishimura; Yoshihide Yamaguchi - Web page: https://patentgrep.com/patent/US6720591B2 ## CPC - H10W 20/494: {changeable by the use of an external beam, e.g. laser beam or ion beam} - H10D 62/117: {Shapes of semiconductor bodies} - H10W 74/129: {forming a chip-scale package [CSP]} - H10B 12/315: {with the capacitor higher than a bit line} - H10B 12/50: {Peripheral circuit region structures} - H10W 70/655: Fan-out layouts - H10W 72/019: {of bond pads} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells. ## Claims ### Claim 1 A semiconductor integrated circuit device comprising: a plurality of memory cells formed on a main surface of a semiconductor chip; a plurality of fuses formed on the main surface of said semiconductor chip; a plurality of multi-layered first wirings formed in an upper layer of said plurality of memory cells; a plurality of internal connection terminals formed of a wiring in the same layer as the uppermost wiring of said plurality of first wirings; a passivation layer formed so as to cover said plurality of first wirings and said plurality of fuses and selectively exposing said plurality of internal connection terminals; a plurality of second wirings formed over said passivation layer, each having one end electrically connected to said internal connection terminal; an uppermost protection layer formed so as to cover said plurality of second wirings and selectively exposing the other ends of said plurality of second wirings; and a plurality of external connection terminals formed on the other ends of said plurality of second wirings, wherein at least a part of said plurality of second wirings are arranged over at least a part of said plurality of fuses, and wherein said passivation layer is formed of an inorganic passivation layer and an organic passivation layer formed on said inorganic passivation layer. ### Claim 2 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein said organic passivation layer and said uppermost protection layer are thicker than said inorganic passivation layer, respectively. ### Claim 3 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein each of said fuses is formed of a part of one of said first wirings. ### Claim 4 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein each of said fuses is formed of a part of a conductive layer included in said memory cells. ### Claim 5 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein said plurality of memory cells are included in a DRAM. ### Claim 6 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein said inorganic passivation layer is formed of a laminated layer of silicon nitride layers or a silicon nitride layer and a silicon oxide layer. ### Claim 7 (depends on 6) The semiconductor integrated circuit device according to claim 6, wherein said organic passivation layer and said uppermost protection layer are thicker than said inorganic passivation layer, respectively. ### Claim 8 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein said organic passivation layer and said uppermost protection layer are made of a dielectric layer mainly formed of polyimide resin, respectively. ### Claim 9 (depends on 8) The semiconductor integrated circuit device according to claim 8, wherein said polyimide resin is a photo-sensitive polyimide resin. ### Claim 10 (depends on 8) The semiconductor integrated circuit device according to claim 8, wherein said organic passivation layer and said uppermost protection layer are thicker than said inorganic passivation layer, respectively. ### Claim 11 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein an elastomer layer is formed on said organic passivation layer and said plurality of second wirings are formed over said elastomer layer. ### Claim 12 (depends on 11) The semiconductor integrated circuit device according to claim 11, wherein said organic passivation layer and said uppermost protection layer are made of a dielectric layer mainly formed of polyimide resin, respectively. ### Claim 13 (depends on 12) The semiconductor integrated circuit device according to claim 12, wherein said polyimide resin is a photo-sensitive polyimide resin. ### Claim 14 (depends on 12) The semiconductor integrated circuit device according to claim 12, wherein said inorganic passivation layer is formed of a laminated layer of silicon nitride layers or a silicon nitride layer and a silicon oxide layer. ### Claim 15 (depends on 11) The semiconductor integrated circuit device according to claim 11, wherein said organic passivation layer and said uppermost protection layer are thicker than said inorganic passivation layer, respectively. ### Claim 16 (depends on 15) The semiconductor integrated circuit device according to claim 15, wherein each of said fuses is formed of a part of a conductive layer included in said memory cells. ### Claim 17 (depends on 15) The semiconductor integrated circuit device according to claim 15, wherein each of said fuses is formed of a part of one of said first wirings. ### Claim 18 A semiconductor integrated circuit device comprising: a plurality of memory cells formed on a main surface of a semiconductor chip; a plurality of fuses formed on the main surface of said semiconductor chip; a plurality of multi-layered first wirings formed in an upper layer of said plurality of memory cells; a plurality of internal connection terminals farmed of a wiring in the same layer as the uppermost wiring of said plurality of first wirings; a passivation layer formed so as to cover said plurality of first wirings and said plurality of fuses and selectively exposing said plurality of internal connection terminals; a plurality of second wirings formed over said passivation layer, each having one end electrically connected to said internal connection terminal; an uppermost protection layer formed so as to cover said plurality of second wirings and selectively exposing the other ends of said plurality of second wirings; and a plurality of external connection terminals formed on the other ends of said plurality of second wirings, wherein at least a part of said plurality of second wirings are arranged over at least a part of said plurality of fuses, and wherein said first wirings are formed of a conductive layer mainly composed of aluminum or copper and said second wirings are formed of a conductive layer mainly composed of copper, respectively. ### Claim 19 A semiconductor integrated circuit device comprising: a plurality of memory cells formed on a main surface of a semiconductor chip; a plurality of fuses formed on the main surface of said semiconductor chip; a plurality of multi-layered first wirings formed in an upper layer of said plurality of memory cells; a plurality of internal connection terminals formed of a wiring in the same layer as the uppermost wiring of said plurality of first wirings; a passivation layer formed so as to cover said plurality of first wirings and said plurality of fuses and selectively exposing said plurality of internal connection terminals; a plurality of second wirings formed over said passivation layer, each having one end electrically connected to said internal connection terminal; an uppermost protection layer formed so as to cover said plurality of second wirings and selectively exposing the other ends of said plurality of second wirings; and a plurality of external connection terminals formed on the other ends of said plurality of second wirings, wherein at least a part of said plurality of second wirings are arranged over at least a part of said plurality of fuses, and wherein each of said external connection terminals is formed of a bump electrode.