# US 6,720,261 B1 · Method and system for eliminating extrusions in semiconductor vias

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- Number: US 6,720,261 B1
- Document ID: US6720261B1
- Status: Granted
- Kind: B1
- Application number: 09/586,586
- Filed: 2000-06-02
- Granted: 2004-04-13
- Earliest claimed: 1999-06-02
- Assignees: Agere Systems Inc.
- Inventors: Steven Mark Anderson; Siddhartha Bhowmik; Joseph William Buckfeller; Sailesh Mansinh Merchant; Frank Minardi
- Web page: https://patentgrep.com/patent/US6720261B1

## CPC

- H10W 20/033: {in openings in dielectrics}
- Y02P 80/30: Reducing waste in manufacturing processes; Calculations of released waste quantities
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.

## Claims

### Claim 1

A method of fabricating vias, comprising:
placing onto a pedestal at least one semiconductor wafer having at least one via adjacent to an interconnect metallization;
controlling the temperature of the interconnect metallization to be less than the temperature at which the interconnection metallization stress transits from a tensile mode to a compressive mode by actively cooling the pedestal; and
depositing a coating to line the via using a low temperature deposition process.

### Claim 2 (depends on 1)

The method of claim 1 wherein the interconnect metallization is selected from the group consisting of: aluminum, aluminum alloys, copper and copper alloys.

### Claim 3 (depends on 1)

The method of claim 1 wherein actively cooling the pedestal comprises transferring heat to a medium flowing through the pedestal.

### Claim 4 (depends on 3)

The method of claim 3 wherein the flowing medium is water.

### Claim 5 (depends on 3)

The method of claim 3 wherein the flowing medium is liquid nitrogen.

### Claim 6 (depends on 3)

The method of claim 3 wherein the flowing medium is helium.

### Claim 7 (depends on 1)

The method of claim 1 wherein the coating is deposited by IMP.

### Claim 8 (depends on 1)

The method of claim 1 wherein the coating comprises two layers.

### Claim 9 (depends on 8)

The method of claim 8 wherein the two layers comprise an adhesion layer and a barrier layer.

### Claim 10 (depends on 8)

The method of claim 8 wherein the two layers arc selected from the group consisting of one or more layers or combinations of: tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, and titanium nitride.

### Claim 11 (depends on 1)

The method of claim 1 wherein the coating comprises three layers.

### Claim 12 (depends on 11)

The method of claim 11 wherein the three layers comprise an adhesion layer, a barrier layer and a seeding layer.

### Claim 13 (depends on 11)

The method of claim 11 wherein the three layers are selected from the group consisting of one or more layers or combinations of: tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride, copper, and copper alloys.

### Claim 14 (depends on 1)

The method of claim 1 wherein the interconnect metallization temperature is no greater than about 100° C.

### Claim 15 (depends on 1)

The method of claim 1 wherein the interconnect metallization temperature is further controlled by decreasing the time for depositing the coating.

### Claim 16 (depends on 15)

The method of claim 15 wherein the interconnect temperature is controlled by decreasing the time for depositing the coating.