Method of forming metal interconnection layer in semiconductor device

Abstract

The present invention relates to a method of forming a metal interconnection layer in a semiconductor device by which a dual damascene pattern, a via hole or a trench having a high aspect ratio is consecutively filled with a metal film without void by means of an electroplating method. For this, the method comprises the steps of forming a lower conductive layer on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate on which the lower conductive layer is formed, selectively etching the interlayer insulating film to form an opening of a given shape through which the lower conductive layer is exposed, forming a metal seed layer along the step on the result in which the opening of the given shape is formed, reflowing the metal seed layer by means of a laser process to form the metal seed layer of an uniform thickness, performing a hydrogen reduction annealing process for the metal seed layer, and forming a metal film on the metal seed layer by means of an electroplating method.

Dependencies are inferred from the claim text.