Pre-pattern surface modification for low-k dielectrics using A H2 plasma
AssigneeTexas Instruments Incorporated
InventorsBrian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
Life of this patent
Estimating the term…
Abstract
A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
Claims11
A method for fabricating an integrated circuit, comprising the steps of:
- forming a low-k dielectric layer over a semiconductor body;
- forming a resist pattern over said low-k dielectric layer, wherein said step of forming a resist pattern further comprises the step of performing a pre-pattern surface modification by treating said low-k dielectric layer with a reducing plasma comprising hydrogen in order to reduce or eliminate resist poisoning;
- and
- etching said low-k dielectric layer using said resist pattern.
A method of fabricating an integrated circuit having copper metal interconnects, comprising the steps of:
- forming an interlevel dielectric (ILD) over a semiconductor body;
- forming an intrametal dielectric (IMD) over the ILD;
- forming a via resist pattern over said IMD wherein said step of forming a via resist pattern further comprises the step of performing a pre-pattern surface modification by plasma treating said IMD using H2 and an inert gas in order to reduce or eliminate resist poisoning;
- etching a via in said IMD and ILD using said via resist pattern;
- removing said via resist pattern;
- at least partially filling said via with a material;
- farming a trench resist pattern aver said IMD;
- etching a trench in said IMD using said trench resist pattern;
- removing said trench resist pattern and said material in said via;
- and
- forming a copper interconnect in said via and said trench.
A method of fabricating an integrated circuit having copper metal interconnects, comprising the steps of:
- forming an interlevel dielectric (ILD) over a semiconductor body;
- forming an intrametal dielectric (IMD) over the ILD;
- performing a first pre-pattern surface modification by treating said IMD with a reducing plasma comprising hydrogen;
- then, forming a vie resist pattern over said IMD;
- etching a via in said IMD using said via resist pattern;
- removing said via resist pattern;
- then, performing a second pre-pattern surface modification by treating said IMD with a reducing plasma comprising hydrogen after removing said via resist pattern;
- then, forming a trench resist pattern over said IMD;
- etching a trench in said IMD using said trench resist pattern;
- removing said trench resist pattern;
- and
- forming a copper interconnect in said via and said trench.
Dependencies are inferred from the claim text.