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US 6,720,227 B1Granted
Method of forming source/drain regions in a semiconductor device
AssigneeAdvanced Micro Devices, Inc.
InventorsDaniel Kadosh, Jon D. Cheek, James F. Buller, Basab Bandyopadhyay
Life of this patent
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Abstract
A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.
Claims34
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing a first ion implantation process using arsenic at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 100 eV-3 keV to partially form source/drain extensions for the device;
- performing a second ion implantation process using arsenic at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 3-7 keV to partially form source/drain extensions for the device;
- and
- performing a third ion implantation process to further form source/drain regions for the device using dopant atoms comprised of at least one of arsenic and phosphorous.
3 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing a first ion implantation process using phosphorous at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 41 eV-1.2 keV to partially form source/drain extensions for the device;
- performing a second ion implantation process using phosphorous at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 1.2-2.9 keV to partially form source/drain extensions for the device;
- and
- performing a third ion implantation process to further form source/drain regions for the device using dopant atoms comprised of at least one of arsenic and phosphorous.
3 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing a first ion implantation process using boron at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 15-440 eV to partially form source/drain extensions for the device;
- performing a second ion implantation process using boron at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 440 eV-1 keV to partially form source/drain extensions for the device;
- and
- performing a third ion implantation process to further form source/drain regions for the device using dopant atoms comprised of at least one of boron and boron difluoride.
3 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing a first ion implantation process using boron difluoride at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 65 eV-2 keV to partially form source/drain extensions for the device;
- performing a second ion implantation process using boron difluoride at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 2-5 keV to partially form source/drain extensions for the device;
- and
- performing a third ion implantation process to further form source/drain regions for the device using dopant atoms comprised of at least one of boron and boron difluoride.
3 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing two ion implantation processes to form source/drain extensions for the device by:
- performing a first ion implantation process using arsenic at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 100 ev-3 keV, and
- performing a second ion implantation process at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 3-7 keV;
- and
- performing a third ion implantation process to further form source/drain regions for the device by:
- performing a third ion implantation process at a dopant concentration level ranging from approximately 5×1014 to 5×1015 ions/cm2.
5 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing two ion implantation processes to form source/drain extensions for the device by:
- performing a first ion implantation process using phosphorous at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 41 eV-1.2 keV, and
- performing a second ion implantation process using phosphorous at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 1.2-2.9 keV;
- and
- performing a third ion implantation process to further form source/drain regions for the device by:
- performing a third ion implantation process at a dopant concentration level ranging from approximately 5×1014 to 5×1015 ions/cm2.
5 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing two ion implantation processes to form source/drain extensions for the device by:
- performing a first ion implantation process using boron at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 15-440 eV, and
- performing a second ion implantation process using boron at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 440 eV-1 keV;
- and
- performing a third ion implantation process to further form source/drain regions for the device by:
- performing a third ion implantation process at a dopant concentration level ranging from approximately 5×1014 to 5×1015 ions/cm2.
5 more elements
A method of forming source/drain regions in a semiconductor device, comprising:
- forming a gate electrode above a semiconducting substrate;
- forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps:
- performing two ion implantation processes to form source/drain extensions for the device by:
- performing a first ion implantation process using boron difluoride at a dopant concentration level ranging from approximately 1×1015 to 1×1016 ions/cm2 and at an energy level ranging from approximately 65 eV-2 keV, and
- performing a second ion implantation process using boron difluoride at a dopant concentration level ranging from approximately 1×1014 to 9×1014 ions/cm2 and at an energy level ranging from approximately 2-5 keV;
- and
- performing a third ion implantation process to further form source/drain regions for the device by:
- performing a third ion implantation process at a dopant concentration level ranging from approximately 5×1014 to 5×1015 ions/cm2.
5 more elements
Dependencies are inferred from the claim text.