# US 6,720,225 B1 · Reactive pre-clean using reducing gas during nickel silicide process

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- Number: US 6,720,225 B1
- Document ID: US6720225B1
- Status: Granted
- Kind: B1
- Application number: 09/679,883
- Filed: 2000-10-05
- Granted: 2004-04-13
- Earliest claimed: 2000-10-05
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Christy Mei-Chu Woo; Minh Van Ngo
- Web page: https://patentgrep.com/patent/US6720225B1

## CPC

- H10P 70/23: {during, before or after processing of insulating materials}
- H10D 30/0212: {using self-aligned silicidation}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; pre-cleaning the sidewall spacers; forming a nickel layer; and forming nickel silicide layers disposed on the source/drain regions and the gate electrode. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The pre-clean uses a hydrogen reactive system in an atmosphere comprising hydrogen and helium. Also, the pre-clean and the formation of the nickel layer are sequentially performed in a single physical vapor deposition chamber system.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising the steps of:
providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions and a gate oxide between the gate electrode and the substrate;
forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls;
pre-cleaning outer surfaces of the first and second sidewall spacers using a reactive system with a reducing gas; and
forming nickel silicide layers disposed on the source/drain regions and the gate electrode, wherein said pre-cleaning step is performed in a first physical vapor deposition chamber, wherein
said pre-cleaning step is performed in an atmosphere comprising hydrogen and helium.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, wherein said nickel silicide forming step includes the step of forming a nickel layer over the substrate and said nickel layer forming step is performed in a second physical vapor deposition chamber.

### Claim 3 (depends on 2)

The method of manufacturing a semiconductor device according to claim 2, wherein said pre-cleaning step and said nickel layer forming step are sequentially performed in a single physical vapor deposition chamber system, which includes the first and second physical vapor deposition chambers.

### Claim 4 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET.

### Claim 5 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, wherein the nickel silicide is formed during a rapid thermal anneal at temperatures from about 380 to 600° C.

### Claim 6 (depends on 5)

The method of manufacturing a semiconductor device according to claim 5, wherein the rapid thermal anneal is performed above 420° C.

### Claim 7

A method of manufacturing a MOSFET semiconductor device, comprising the steps of:
providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions and a gate oxide between the gate electrode and the substrate;
forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls;
pre-cleaning outer surfaces of the first and second sidewall spacers using a hydrogen reactive system in an atmosphere comprising hydrogen and helium;
forming a nickel layer over the substrate; and
forming nickel silicide layers disposed on the source/drain regions and the gate electrode during a rapid thermal anneal at temperatures from about 380 to 600° C.,
wherein said pre-cleaning step and said nickel layer forming step are sequentially performed in a single physical vapor deposition chamber system.