# US 6,720,222 B2 · Method of manufacturing semiconductor device

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- Number: US 6,720,222 B2
- Document ID: US6720222B2
- Status: Granted
- Kind: B2
- Application number: 10/271,589
- Filed: 2002-10-17
- Published: 2003-05-01
- Granted: 2004-04-13
- Earliest claimed: 2001-10-26
- Assignees: Seiko Epson Corporation
- Inventors: Atsushi Kanda; Yasushi Haga
- Web page: https://patentgrep.com/patent/US6720222B2

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be formed efficiently on an identical substrate without damaging the characteristics of the respective MOS transistors.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, in which both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor having different drain breakdown voltages are formed on an identical semiconductor substrate, the manufacturing method comprising the steps of:
(a) forming a gate electrode on a first dielectric film created above the substrate, creating a second dielectric film over surface of the substrate including the gate electrode, and etching the second dielectric film, so as to define a side wall of the second dielectric film on a side face of the gate electrode; and
(b) implanting an impurity to specify a drain area and a source area, the step (b) comprising the sub-steps of:
(b-1) forming a first mask that keeps open at least a drain-source forming region in the high-breakdown-voltage MOS transistor, which is expected to form a drain area and a source area, and covers over at least an offset forming region in the high-breakdown-voltage MOS transistor, which is expected to form an offset area between the gate electrode and either one of the drain area and the source area;
(b-2) using the first mask and etching off a dielectric film part at least on the drain-source forming region, out of the dielectric film created on the substrate; and
(b-3) continuously using the same first mask and implanting the impurity into the drain-source forming region.

### Claim 2 (depends on 1)

A manufacturing method in accordance with claim 1, wherein the step (a) creates the second dielectric film in a greater thickness than a predetermined standard thickness,
the sub-step (b-1) forming the first mask that keeps open an element forming region in the low-breakdown-voltage MOS transistor, on which an element is to be generated, in addition to the drain-source forming region,
the sub-step (b-3) implanting the impurity into the element forming region as well as into the drain-source forming region.

### Claim 3 (depends on 2)

A manufacturing method in accordance with claim 2, wherein the predetermined standard thickness is approximately 1300 angstrom.

### Claim 4 (depends on 1)

A manufacturing method in accordance with claim 1, wherein the sub-step (b-1) forms the first mask that covers over an element forming region in the low-breakdown-voltage MOS transistor, on which an element is to be generated, in addition to the offset forming region,
the step (b) further comprising the sub-steps of:
(b-4) forming a second mask that keeps open at least the element forming region in the low-breakdown-voltage MOS transistor; and
(b-5) using the second mask and implanting the impurity into at least the element forming region.

### Claim 5 (depends on 1)

A manufacturing method in accordance with claim 1, the manufacturing method further comprising the step of:
(c) forming a metal film on the gate electrode, the drain area, and the source area and carrying out heat treatment, so that at least part of semiconductor layers constructing the gate electrode, the drain area, and the source area is fused to a metal of the metal film and is thereby silicidated,
the step (c) comprising the sub-step of:
(c-1) generating a protective film at least over the offset forming region.

### Claim 6 (depends on 2)

A manufacturing method in accordance with claim 2, the manufacturing method further comprising the step of:
(c) forming a metal film on the gate electrode, the drain area, and the source area and carrying out heat treatment, so that at least part of semiconductor layers constructing the gate electrode, the drain area, and the source area is fused to a metal of the metal film and is thereby silicidated,
the step (c) comprising the sub-step of:
(c-1) generating a protective film at least over the offset forming region.

### Claim 7 (depends on 3)

A manufacturing method in accordance with claim 3, the manufacturing method further comprising the step of:
(c) forming a metal film on the gate electrode, the drain area, and the source area and carrying out heat treatment, so that at least part of semiconductor layers constructing the gate electrode, the drain area, and the source area is fused to a metal of the metal film and is thereby silicidated,
the step (c) comprising the sub-step of:
(c-1) generating a protective film at least over the offset forming region.

### Claim 8 (depends on 4)

A manufacturing method in accordance with claim 4, the manufacturing method further comprising the step of:
(c) forming a metal film on the gate electrode, the drain area, and the source area and carrying out heat treatment, so that at least part of semiconductor layers constructing the gate electrode, the drain area, and the source area is fused to a metal of the metal film and is thereby silicidated,
the step (c) comprising the sub-step of:
(c-1) generating a protective film at least over the offset forming region.