Method for forming a programmable decoder with vertical transistors

A method for forming a decode circuit for a semiconductor memory, comprising:

• forming a number of address lines;
• forming a number of output lines;
• wherein forming the address lines, and the output lines includes forming an array;
• forming a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• forming a pair of single crystalline ultra thin vertical floating gate transistors on opposing sides of each pillar, wherein forming each single crystalline vertical floating gate transistor includes;
• depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
• annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
• wherein the annealing causes the single crystalline first contact layer and the second contact layer of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type;
• and
• forming a floating gate opposing the vertical body region in a trench and separated therefrom by a tunnel oxide;
• and
• wherein forming each of the number of address lines includes forming the number of address lines disposed between rows of the pillars such that each address line is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.

A method for forming a memory address decoder, comprising:

• forming a number of address lines;
• forming a number of output lines;
• wherein forming the address lines, and the output lines includes forming an array;
• forming a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• forming a pair of single crystalline ultra thin vertical floating gate transistors along opposing sides of each pillar, wherein forming each single crystalline vertical floating gate transistor includes;
• depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
• annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
• wherein the annealing causes the single crystalline first contact layer and the second contact layer of the first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type;
• and
• forming a floating gate opposing the vertical body region and separated therefrom by a gate oxide;
• and
• wherein forming each of the number of address lines includes forming each of the number of address lines disposed in a trench between rows of the pillars such that each address line is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.

A method of forming a decoder, the method comprising:

• forming a number of vertical pillars extending outwardly from a substrate;
• forming a number of vertically-oriented single crystalline layers, including forming each single crystalline layer on a side of one of the vertical pillars to have a thickness of less than 10 nanometers extending from and normal to the side of the pillar;
• forming a first source/drain region, a body region, and a second source/drain region in each single crystalline layer, the body region being disposed between the first and second source/drain regions;
• forming a floating gate adjacent to and separated from the body region by a floating gate oxide;
• forming a number of address lines, including forming each address line adjacent to and separated from a number of the floating gates by a control gate insulator;
• forming a number of data lines, including electrically connecting each data line to one of the first and second source/drain regions for a number of the single crystalline layers;
• and
• selectively connecting the number of address lines and the number of data lines to the single crystalline layers to implement a desired logic function that selects one of the data lines as a function of an address provided on the address lines and a charge stored on the floating gates.

A method of forming a decoder, the method comprising:

• forming a number of vertical pillars extending outwardly from a substrate;
• forming a number of vertically-oriented single crystalline layers, including forming each single crystalline layer on a side of one of the vertical pillars, including:
• forming a polysilicon layer on the side of the vertical pillar;
• and
• annealing the polysilicon layer to form the single crystalline layer through a solid phase epitaxt process;
• forming a first source/drain region, a body region, and a second source/drain region in each single crystalline layer, the body region being disposed between the first and second source/drain regions;
• forming a floating gate adjacent to and separated from the body region by a floating gate oxide;
• forming a number of address lines, including forming each address line adjacent to and separated from a number of the floating gates by control gate insulator;
• forming a number of data lines, including electrically connecting each data line to one of the first and second source/drain regions for a number of the single crystalline layers;
• and
• selectively connecting the number of address lines and the number of data lines to the single crystalline layers to implement a desired logic function that selects one of the data lines as
• a function of an address provided on the address lines and a charge stored on the floating gates.

A method of forming a decoder, the method comprising:

• forming a number of vertical pillars extending outwardly from a substrate;
• forming a number of vertically-oriented single crystalline layers, including forming single crystalline layer on a side of one of the vertical pillars to have a vertical length of less than 100 nanometers and a thickness of less than 10 nanometers extending from and normal to the side of the pillar;
• forming a first source/drain region, a body region, and a second source/drain region in each single crystalline layer, the body region being disposed between the first and second source/drain regions;
• forming a floating gate adjacent to and separated from the body region by a floating gate oxide;
• forming a number of address lines, including forming each address line adjacent to and separated from a number of the floating gates by a control gate insulator;
• forming a number of data lines, including electrically connecting each data line to one of the first and second source/drain regions for a number of the single crystalline layers;
• and
• selectively connecting the number of address lines and the number of data lines to the single crystalline layers to implement a desired logic function that selects one of the data lines as a function of an address provided on the address lines and a charge stored on the floating gates.

A method of forming a decoder, the method comprising:

• forming a number of vertical pillars extending outwardly from a substrate;
• forming a number of vertically-oriented single crystalline, including forming each single crystalline layer on side of one of the vertical pillars to have a vertical length of less than 100 nanometers and a thickness of less than 10 nanometers extending from and normal to the side of the pillar, including:
• forming a polysilicon layer on the side of the vertical pillar;
• and
• annealing the polysilicon layer to form the single crystalline layer through a solid
• phase epitaxy process;
• forming a first source/drain region, a body region, and a second source/drain region in each single crystalline layer, the body region being disposed between the first and second source/drain regions;
• forming a floating gate adjacent to and separated from the body region by a floating gate oxide;
• forming a number of address lines, including forming each address line adjacent to and separated from a number of the floating gates by a control gate insulator;
• forming a number of data lines, including electrically connecting each data line to one of the first and second source/drain regions for a number of the single crystalline layers;
• and
• selectivity connecting the number of address lines and the number of data lines to the single crystalline layers to implement a desired logic function that selects one of the data lines as a function of an address lines and a charge stored on the floating gates.

A method of forming a decoder, the method comprising:

• forming a number of vertical pillars extending outwardly from a substrate, including:
• forming a single crystalline first contact layer with a first dopant of a first
• conductivity type on the substrate;
• forming an oxide layer on the first contact layer;
• and
• forming a second contact layer with a second dopant of the first conductivity type
• on the oxide layer;
• forming a polysilicon layer with a third dopant of a second conductivity type on the side of the vertical pillar in contact with the first contact layer, the oxide layer and the second contact layer;
• annealing a structure including the substrate and the polysilicon layer, wherein:
• the single crystalline first contact layer seeds a crystalline growth in the
• polysilicon layer, and the polysilicon layer is recrystallized into a
• vertically-oriented single crystalline layer using a solid phase epitaxial process;
• the first dopant of the first contact layer is diffused onto the vertically-oriented
• single crystalline layer to form a first source/drain region, and the second
• dopant of the second contact layer is diffused into the vertically-oriented
• single crystalline layer to form a second source/drain region;
• and a body a region is formed by the vertically-oriented single crystalline layer with the
• third dopant of a second conductivity type;
• forming a floating gate adjacent to and separated from the body region by a floating gate oxide;
• forming a number of address lines, including forming each address line adjacent to and separated from a number of the floating gates by a control gate insulator;
• forming a number of data lines, including electrically connecting each data line to one of the first and second source/drain regions for a number of the single crystalline layers;
• and
• selectivity connecting the number of address lines and the number of data lines to the single crystalline layers to implement a desired logic function that selects one of the data lines as a function of an address provided on the address lines and a charge stored on the floating gates.