Method of eliminating back-end rerouting in ball grid array packaging

A method of chip scale packaging, comprising the steps of:

• providing a semiconductor die having internal metal lines formed therein, wherein said internal metal lines comprise metallic damascene layers, and wherein a final metal layer of the internal metal lines comprises at least one exposed region on a surface of the semiconductor die;
• depositing an insulative layer over the surface of the semiconductor die;
• etching through said insulative layer so as to provide an opening to said exposed region of said final metal layer of said internal metal lines;
• depositing a passivation layer over said insulative layer;
• depositing a compliant material layer over said passivation layer;
• etching through said compliant material and said passivation layer so as to provide an opening to said exposed region of said final metal layer of said internal metal lines;
• depositing a substantially homogenous conductive layer;
• patterning said substantially homogenous conductive layer to form a conductor comprising a pad disposed on said compliant layer, wherein the conductor electrically contacts said exposed region of said final metal layer of said internal metal lines so as to provide a direct electrical connection between the pad and said final metal layer;
• and
• forming a solder bail upon said pad.