# US 6,720,199 B2 · Method for manufacturing TFT array substrate of liquid crystal display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,720,199 B2 - Document ID: US6720199B2 - Status: Granted - Kind: B2 - Application number: 10/088,943 - Filed: 2002-03-21 - Published: 2002-10-17 - Granted: 2004-04-13 - Earliest claimed: 2000-07-24 - Assignees: Advanced Display Inc. - Inventors: Ryouta Matsubara - Web page: https://patentgrep.com/patent/US6720199B2 ## CPC - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/13629: {Multilayer wirings} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A semiconductor layer protruding beside a source line is removed in order to increase aperture ratio, decrease resistance of the source line and prevent source-common capacitance from increasing. When a part of a passivation film is removed to form a contact hole, the passivation film on the source line, the passivation film beside the source line and a gate insulating layer beside the source line are simultaneously removed. A portion protruding beside the source line is removed from thus exposed semiconductor layer using a resist pattern for removing the part of the passivation film and/or the source line as a mask. ## Claims ### Claim 1 A method for manufacturing a TFT array substrate in which at least (a) a gate insulating film, (b) a semiconductor layer and (c) a metal layer are sequentially formed in this order of (a), (b) and (c), and using one resist pattern formed by a photolithography, a part of the metal layer is selectively removed, to form a source line, together with the semiconductor layer beside the source line, wherein a passivation film is formed after the formation of the source line and the removal of the semiconductor layer beside the source line, a resist pattern to selectively remove the passivation film is formed on the passivation film, and using the resist pattern, the passivation film above the source line, the passivation film beside the source line and the gate insulating film beside the source line are removed to, thereby, expose the semiconductor layer under the source line. ### Claim 2 (depends on 1) A method for manufacturing a TFT array substrate according to claim 1, wherein a portion protruding beside the source line is removed from the exposed semiconductor layer under the source line through etching utilizing the resist pattern to selectively remove the passivation film and/or the source line as a mask. ### Claim 3 (depends on 1) A method for manufacturing a TFT array substrate according to claim 1, wherein a portion protruding beside the source line is removed from the exposed semiconductor layer under the source line through etching utilizing the selectively removed passivation film and/or the source line as a mask. ### Claim 4 (depends on 1) A method for manufacturing a TFT array substrate according to claim 1 wherein a ITO film is further formed, and through patterning to selectively remove the ITO film, the ITO film on the source line is left to form the ITO film covering the source line. ### Claim 5 A method for manufacturing a TFT array substrate in which as least (a) a gate insulating film, (b) a semiconductor layer and (c) a metal layer are sequentially formed in this order of (a), (b) and (c), and using one resist pattern formed by a photolithography, a part of the metal layer is selectively removed, to form a source line, together with the semiconductor layer beside the source line, wherein no passivation film is formed after the formation of the source line and the removal of the semiconductor layer beside the source line. ### Claim 6 (depends on 5) A method for manufacturing a TFT array substrate according to claim 5 wherein the removal of the semiconductor layer beside the source line is accomplished such that the source line and the semiconductor layer under the source line remain exposed, and a portion protruding beside the source line is removed from the exposed semiconductor layer under the source line through etching utilizing the source line as a mask. ### Claim 7 (depends on 5) A method for manufacturing a TFT array substrate according to claim 5 wherein a ITO film is further formed, and through patterning to selectively remove the ITO film, the ITO film on the source line is left to form the ITO film covering the source line. ### Claim 8 A method for manufacturing a TFT array substrate in which at least (a) a gate insulating film, (b) a first semiconductor layer, (c) a second semiconductor layer and (d) a metal layer are sequentially formed in this order of (a), (b), (c) and (d), and a resist pattern comprising a region in which photoresist is removed, a region in which photoresist has a small thickness and a region in which photoresist has a great thickness is further formed by means of a photolithography, wherein the metal layer, the second semiconductor layer and the first semiconductor layer are removed in the region in which photoresist is removed, the metal layer and the second semiconductor layer are removed in the region in which photoresist has a small thickness, and the metal layer, the second semiconductor layer and the first semiconductor layer are left remained in the region in which photoresist has a great thickness to form a source line with the metal layer left remained, and wherein a region adjacent to the source line is the region in which photoresist has a small thickness, so that the metal layer and the second semiconductor layer are removed and the first semiconductor layer is left remained. ### Claim 9 (depends on 8) A method for manufacturing a TFT array substrate according to claim 8 wherein a passivation film is formed after removal of the photoresist, a resist pattern to selectively remove the passivation film is formed on the passivation film, and using the resist pattern, the passivation film above the source line and the passivation film beside the source line are removed to, thereby, expose the second and first semiconductor layers under the source line. ### Claim 10 (depends on 8) A method for manufacturing a TFT array substrate according to claim 8 wherein a ITO film is further formed, and through patterning to selectively remove the ITO film, the ITO film on the source line is left to form the ITO film covering the source line. ### Claim 11 (depends on 9) A method for manufacturing a TFT array substrate according to claim 9 wherein a portion protruding beside the source line is removed from the exposed second and first semiconductor layers under the source line through etching utilizing the resist pattern to selectively remove the passivation film and/or the source line as a mask. ### Claim 12 (depends on 9) A method for manufacturing a TFT array substrate according to claim 9 wherein a portion protruding beside the source line is removed from the exposed second and first semiconductor layers under the source line through etching utilizing the selectively removed passivation film and/or the source line as a mask. ### Claim 13 A method for manufacturing a TFT array substrate in which at least (a) a gate insulating film, (b) a first semiconductor layer, (c) a second semiconductor layer and (d) a metal layer are sequentially formed in this order of (a), (b), (c) and (d), and a resist pattern comprising a region in which photoresist is removed, a region in which photoresist has a small thickness and a region in which photoresist has a great thickness is further formed by means of a photolithography, wherein the metal layer, the second semiconductor layer and the first semiconductor layer are removed in the region in which photoresist is removed, the metal layer and the second semiconductor layer are removed in the region in which photoresist has a small thickness, and the metal layer, the second semiconductor layer and the first semiconductor layer are left remained in the region in which photoresist has a great thickness to form a source line with the metal layer left remained, wherein a region adjacent to the source line is the region in which photoresist has a small thickness, so that the metal layer and the second semiconductor layer are removed and the first semiconductor layer is left remained, and wherein no passivation film is formed after removal of the resist pattern. ### Claim 14 (depends on 13) A method for manufacturing a TFT array substrate according to claim 13 wherein a portion protruding beside the source line is removed from the second and first semiconductor layers under the source line through etching utilizing the source line as a mask. ### Claim 15 (depends on 14) A method for manufacturing a TFT array substrate according to claim 14 wherein a ITO film is further formed, and through patterning to selectively remove the ITO film, the ITO film on the source line is left to form the ITO film covering the source line. ### Claim 16 (depends on 14) A method for manufacturing a TFT array substrate according to claim 14 wherein a photoresist on a lower electrode pad at the end of the gate line is removed through a peripheral exposing step in which no mask is used, so that a part of the gate insulating film is removed by etching to expose the lower electrode pad at the end of the gate line.