Fail-safe circuit for dynamic smartpower integrated circuits
AssigneeXerox Corporation
InventorsJuan J. Becerra, William G. Hawkins, Christopher R. Morton, Yungran Choi
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Abstract
A method and Apparatus for protection of semiconductor micromechanical devices that use circuits with dynamic logic addressing is disclosed. In one exemplary embodiment of the invention, a fail-safe circuit is provided for an ink jet print head integrated circuit which prevents a catastrophic consequence of the dynamic logic addressed integrated circuit losing its charge.
Claims19
A dynamic fail-safe circuit usable to reduce a likelihood of damage to a circuit that includes a dynamic logic circuit, the dynamic logic circuit having a particular hold time τhd and a nominal refresh time τr shorter than the hold time τhd, upon the dynamic logic circuit losing state, comprising:
- a dynamic timer circuit having a hold time τhf, where τr<τhf<τhd.
A method of protecting a dynamic logic circuit wherein the dynamic logic circuit having a particular hold time τhd and a refresh time τr shorter than the hold time τhd, comprising:
- adjusting the dynamic timer circuit having a hold time τhf, and a maximum allowable hold time τhf such that τr<τhf<τhd.
A method for protecting an ink jet print head having at least one drop ejector array and a transistor array, comprising:
- driving the at least one drop ejector array with a dynamic logic circuit having a particular hold time τhd and a refresh time τr shorter than the hold time;
- and
- coupling a fail-safe circuit to the dynamic logic circuit, that measures the refresh time τr and enables the transistor array only when the refresh time τr is less than the hold time τhd.
A fail-safe circuit for an ink jet print head having at least one drop ejector array;
- a transistor array for driving the at least one drop ejector array;
- a dynamic logic circuit having a particular hold time τhd and a refresh time τr shorter than the hold time;
- and
- a fail-safe circuit, coupled to the dynamic logic circuit, that detects the failure of the logic circuit to be refreshed and sends a disable signal to the transistor circuit in a time τdf before (1) the logic signal detects its failure to be refreshed and (2) a signal indicative of the failure to be refreshed arrives at the transistor array in a time τdd.
A method for protecting an ink jet print head having at least one drop ejector array, a transistor array for driving the at least one drop ejector array, and a dynamic logic circuit having a particular hold time τhd and a refresh time τr shorter than the hold time, comprising:
- p1 detecting the failure of the logic circuit to be refreshed and
- sending a disable signal to the transistor circuit in a time τdf before the logic signal detects its failure to be refreshed and a signal indicative of the failure to be refreshed arrives at the transistor array in a time τdd.
An ink jet printing system including a printer with at least one source of ink, a scanning carriage, substrate feeder and dynamic print head control circuitry, comprising:
- a dynamic fail-safe circuit usable to reduce a likelihood of damage to a circuit that includes a dynamic logic circuit, the dynamic logic circuit having a particular hold time τhd and a nominal refresh time τr shorter than the hold time τhd, upon the dynamic logic circuit losing state with a dynamic timer circuit having a hold time τhf, where τr<τhf<τhd.
Dependencies are inferred from the claim text.