Substrate with top-flattened solder bumps and method for manufacturing the same

A method for manufacturing a wiring substrate having a main surface, a back surface, and a plurality of top-flattened solder bumps projecting from the main surface, said method comprising the steps of:

• forming a solid layer on a core substrate so as to partially cover the core substrate;
• forming at least one resin dielectric layer on the solid layer and the core substrate;
• forming a plurality of pads on the resin dielectric layer in such a manner that the plurality of pads are exposed at the main surface of the wiring substrate, the pads including first pads located within a region above the solid layer and second pads located outside of said region;
• applying, through printing, solder paste onto each of the plurality of pads such that a decreased amount of solder paste is applied onto each of the first pads as compared with that applied onto each of the second pads;
• melting the applied solder paste, through reflowing, so as to form substantially hemispherical solder bumps;
• and
• flattening top portions of the substantially hemispherical solder bumps through pressing of a flat pressing surface against top portions of the substantially hemispherical solder bumps so as to thereby form the top-flattened solder bumps.