Method for building a real-time control system with mode and logical rate

A method of mapping a thread of a processor to components within a control system, wherein said control system comprises a plurality of components in a multi-level hierarchy, said method comprising:

• a. defining one or more logical rates of execution at each level in said multi-level hierarchy;
• b. for each component in a level of said multi-level hierarchy, assigning said component to one or more of said logical rates;
• and
• c. mapping said thread of said processor to one or more of said logical rates, thus mapping said thread through said multi-level hierarchy, resulting in a system of components, executing at the actual execution rate of said thread.

A method of defining an executable image for a multi-level hierarchy control system comprising a plurality of components, said method comprising

• a. choosing a subset of said components to correspond to said executable image;
• b. identifying a name for said executable image and its corresponding subset of said components;
• and
• c. for each chosen component in said subset, indicating that said component is part of said executable image for said multi-level hierarchy control system, whereby when said executable image is produced for said multi-level hierarchy control system, only said subset of said components that correspond to said executable image will be included.

A method of defining an executable image for a control system, wherein said control system comprises a multi-level hierarchy, said method further comprising:

• a. defining at least one logical executable name or designator at each level;
• b. choosing a subset of components at each level to correspond to each said logical executable name;
• c. for each chosen component in each subset, indicating that said component is part of said logical executable name;
• d. continuing this process throughout the hierarchy, thus assigning components to logical executable names at each level;
• and
• e. mapping said executable image to said logical executable names throughout said multi-level hierarchy such that only the subset of said components assigned to the mapped said logical executable names will be included in the executable image.