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US 6,718,440 B2Granted
Memory access latency hiding with hint buffer
AssigneeIntel Corporation
InventorsSubramaniam Maiyuran, Vivek Garg, Mohammad A. Abdallah, Jagannath Keshava
Life of this patent
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Abstract
A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.
Claims23
A method comprising:
- receiving a read request to fetch data and/or one or more instructions;
- accessing a primary cache memory to retrieve the requested data and/or one or more instructions in response to the read request;
- accessing a secondary cache memory to retrieve the requested data and/or one or more instructions if there is a cache miss in the primary cache memory;
- substantially concurrently issuing a request hint to fetch the requested data and/or one or more instructions from a main memory while accessing the secondary cache memory and storing the fetched data and/or one or more instructions in a hint buffer;
- and
- if the requested data and/or instruction(s) are not in the secondary cache memory, returning the data and/or instruction(s) from the hint buffer.
3 more elements
An apparatus comprising:
- a primary cache memory;
- a secondary cache memory;
- logic coupled to the primary cache memory and the secondary cache memory to access the primary cache memory to retrieve data and/or instruction(s) in response to a read request for the data and/or instruction(s), to accessing the secondary cache memory if the requested data and/or instruction(s) are not in the primary cache memory, and to substantially concurrently issue a request hint to accessing a main memory to fetch the requested data and/or instruction(s) while accessing the secondary cache memory;
- and
- a memory controller coupled to the logic and comprising a limit buffer, the memory controller to receive the request hint and to access the main memory to fetch data and/or one or more instructions in response to the request hints to store the accessed data and/or instruction(s) in the hint buffer, and to return to the logic the accessed data and/or instruction(s) from the hint buffer.
2 more elements
A system comprising:
- main memory;
- cache memory including a primary cache memory and a secondary cache memory;
- logic coupled to the cache memory to request data and/or one or more instructions from the primary cache memory in response to a read request, to access the secondary cache memory if the requested data and/or one or more instructions are not in the primary cache memory, and substantially concurrently to issue a request hint to access the main memory to fetch the requested data and/or one or more instructions while accessing the secondary cache memory;
- and
- a memory controller coupled to the logic and to the main memory and comprising a hint buffer, the memory controller to receive the request hint and to access the main memory to fetch data and/or one or more instructions in response to the request hint and store the accessed data and/or instruction(s) in the hint buffer, the memory controller to return to the logic the accessed data and/or instruction(s) from the hint buffer in response to the request hint.
2 more elements
Dependencies are inferred from the claim text.