Non-volatile semiconductor memory device with cache function and program, read, and page copy-back operations thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Seok Byeon, Young-Ho Lim
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device according to embodiments of the invention includes a page buffer acting as a sense amplifier during a read operation and as a write driver during a program operation. The page buffer has two sense and latch blocks, which exclusively carry out the same function. While one of the sense and latch blocks carries out a read operation, the other sense and latch block outputs previously sensed data to the exterior. Further, while one of the sense and latch blocks carries out a program operation, the other sense and latch block loads data to be programmed. Due to the page buffer, an operation speed of the non-volatile memory device can be enhanced.
Claims36
A semiconductor memory device comprising:
- an array including a plurality of wordlines, at least two bitlines, and a plurality of memory cells each being arranged at intersections of the wordlines and the bitlines;
- a register including first and second sense and latch blocks commonly coupled to an internal node;
- and
- a data bus coupled to the internal node;
- wherein the first and second sense and latch blocks are structured to independently and exclusively perform a read/program operation for corresponding bitlines;
- and
- wherein the memory device is structured to sense/program data from/to a memory cell by the first sense and latch block while data is loaded/outputted to/from the second sense and latch block from/to the data bus.
A non-volatile semiconductor memory device comprising:
- a memory cell array including a plurality of cell strings each being electrically connected to corresponding their bitlines, wherein among the corresponding bitlines, two adjacent bitlines constitute a bitline pair;
- a plurality of unit page buffers each being coupled to the bitline pairs;
- and
- a column gate circuit for selecting at least one of the unit page buffers to couple the selected unit page buffer to a data bus,
- wherein each of the unit page buffers includes:
- a sense node,
- an internal node coupled to the data bus via the column gate circuit,
- a bitline select and bias block for selecting one of bitlines of a corresponding pair to couple the selected bitline to the sense node,
- a precharge block for charging the sense node in response to a precharge control signal,
- a first sense and latch block coupled between the sense node and the internal node, and
- a second sense and latch block coupled between the sense node and the internal node,
- wherein the first and second sense and latch blocks are structured to independently and exclusively perform a read/program operation for bitlines of a corresponding pair;
- and
- wherein, while one of the first and second sense and latch blocks senses/programs data from/to a memory cell, data is loaded/outputted to/from the other sense and latch block via the switch circuit.
A method of programming data in a non-volatile semiconductor memory device comprising a memory cell array, a plurality of unit page buffers, and a column gate circuit for selecting at least one of the unit page buffers to couple the selected unit page buffer to a data bus, the method comprising:
- loading data to a first sense and latch block of the selected unit page buffer;
- using the data in the first sense and latch block to carry out a first program operation and concurrently to load data to a second sense and latch block of the selected unit page buffer;
- and
- using the data in the second sense and latch block to carry out a second program operation and concurrently to load data to the first sense and latch block.
A method for reading data in a non-volatile semiconductor memory device comprising a memory cell array, including a plurality of cell strings each being electrically connected to corresponding their bitlines, wherein among the corresponding bitlines, two adjacent bitlines constitute a bitline pair;
- a plurality of unit page buffers each being coupled to the bitline pairs;
- and a column gate circuit for selecting at least one of the unit page buffers to couple the selected unit page buffer to a data bus, the method comprising:
- sensing data from the memory cell array via one of a pair of bitlines corresponding to the selected unit page buffer;
- latching the sensed data to a first sense and latch block of the selected unit page buffer;
- outputting the data in the first sense and latch block to the exterior of the memory device and concurrently sensing data from the memory cell array via the other bitline corresponding to the selected unit page buffer, and
- latching the sensed data to a second sense and latch block of the selected unit page buffer.
A copy-back method in a non-volatile semiconductor memory device comprising a memory cell array including a plurality of cell strings each being electrically connected to corresponding their bitlines, wherein among the corresponding bitlines, two adjacent bitlines constitute a bitline pair, and each of the cell strings has memory cells each being coupled to corresponding their wordlines;
- a plurality of unit page buffers each being coupled to the bitline pairs;
- and a column gate circuit for selecting at least one of the unit page buffers to couple the selected unit page buffer to a data bus, the method comprising:
- sensing data from memory cells coupled to a selected one of the wordlines,
- latching the sensed data in a first or second sense and latch block of the respective unit page buffers;
- and
- programming the data latched in the first or second sense and latch block to memory cells of the wordlines except the selected one of the wordlines,
- wherein the latched data has the same state as the programmed data.
Dependencies are inferred from the claim text.