Method of resolving min-time violations in an integrated circuit
AssigneeHewlett-Packard Development Company, L.P.
InventorDimitri C. Argyres
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AssigneeHewlett-Packard Development Company, L.P.
InventorDimitri C. Argyres
Estimating the term…
A method is disclosed for resolving timing violations in a circuit design by adding de-racing buffers that slow selected signals to ensure that the signals do not arrive at a recipient state element too soon. A circuit design stored in memory has data including connectivity and timing information. This information is extracted to identify state elements with paths having min-time violations. The method attempts to resolve the min-time violations by inserting a de-racer at an instance at the end of the path, nearest the recipient state element. If the de-racer cannot be added, the method backtraces upstream along the path to the inputs of the next circuit element. The method attempts to de-race the instance by determining whether a de-racer would create a critical path. If any of the instances of the inputs cannot be de-raced, then the method backtraces again to the next upstream circuit element.
A method for testing an integrated circuit design to resolve min-time violations, comprising:
A method for resolving min-time violations in an integrated circuit design, comprising:
A method for resolving min-time violations in an integrated circuit, comprising:
Dependencies are inferred from the claim text.