Method of testing a semiconductor memory device

A method for testing a semiconductor memory device, wherein said method tests a semiconductor memory device having a wide data bus of an (m×n)-bit width and includes a first process and a second process,

• said first process comprising the steps of:
• inputting (m×n)-bit data;
• writing the (m×n)-bit data into each address of the semiconductor memory device;
• reading out (m×n)-bit data written into each address of said semiconductor memory device;
• comparing the read-out (m×n)-bit data with the input (m×n)-bit data of its before-written state to determine whether the read-out (m×n)-bit data is correct;
• obtaining, if it is determined that the read-out (m×n)-bit data is erroneous, an address corresponding to the erroneous data as a defective address;
• and
• ending testing of the semiconductor memory device if it is determined that the read-out (m×n)-bit data from all addresses of said semiconductor memory device is correct;
• and
• said second process comprising the steps of:
• writing (m×n)-bit data into said obtained defective address and then reading out the written (m×n)-bit data;
• dividing the read-out (m×n)-bit data into pieces each having a number of bits smaller than m×n and larger than m;
• comparing each piece of the divided read-out data having said number of bits with a corresponding piece of data obtained as a result of dividing said (m×n)-bit data of its before-written state into pieces each having said number of bits to determine whether the each piece of the divided read-out data is correct;
• and
• comparing each m-bit data constituting an erroneous piece of the divided read-out data having said number of bits with an expected value of a predetermined m-bit data to determine whether the each m-bit data constituting the erroneous piece of the divided read-out data is correct.