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US 6,715,114 B2Granted
Test method and apparatus for semiconductor device
AssigneeFujitsu Limited
InventorNaoyuki Koike
Life of this patent
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Abstract
A semiconductor device testing apparatus includes a first part which repeatedly performs a wafer-level burn-in to chips formed on a wafer, and a second part which detects a progress of occurrence of faulty cells in each of the chips.
Claims18
A semiconductor device testing apparatus comprising:
- a first part which repeatedly performs a wafer-level burn-in to chips formed on a wafer up to n times, where n is an integer obtained by dividing a total burn-in time into n parts;
- and
- a second part which detects a change of a number of faulty cells with time in each of the chips.
A method of testing a semiconductor device comprising the steps of:
- (a) repeatedly performing a wafer-level burn-in to chips formed on a wafer up to n times, where n is an integer obtained by dividing a total burn-in time into n parts;
- and
- (b) detecting a change of a number of faulty cells with time in each of the chips.
Dependencies are inferred from the claim text.