Feedback system and method for optimizing the reception of multidimensional digital frame structure communications
AssigneeApplied Micro Circuits Corporation
InventorsGeorge Beshara Bendak, Alan Michael Sorgi, Daniel M. Castagnozzi
Life of this patent
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Abstract
A system and method are provided for using an analysis of forward error corrections (FEC) in a digital communications signal as feedback information to improve the performance of an analog receiver system. The FEC decoder supplies the number of “1” bit and “0” bit corrections made to a control unit. In response to the FEC corrections, the control unit changes receiver control parameters. The control signal modifies processing in the receiver front end to achieve the fewest number of FEC corrections.
Claims16
A method for optimizing the reception of digital communications, the method comprising:
- receiving digital communication including forward error correction (FEC) sections;
- processing the received communications;
- determining errors in response to making forward error corrections;
- and
- adjusting the processing in response to determining errors;
- wherein determining errors in response to making forward error corrections includes:
- comparing the number of “1” bits corrected to the number of “0” bits corrected;
- wherein adjusting the processing in response to determining errors includes adjusting the processing in response to the comparison of “1” bit and “0” bit corrections;
- wherein receiving digital communications including forward error correction (FEC) sections includes receiving a signal having a first polarity associated with “1” bits, and a second polarity associated with “0” bits;
- and
- wherein adjusting the processing in response to determining errors includes supplying a modified communication signal with a signal swing adjusted between the first and second polarities.
A system for optimizing the reception of digital communications, the system comprising:
- a processor having a first input to accept a communication signal including forward error correction (FEC) sections, and a second input to accept control signals, the processor supplying a modified communication signal at an output in response to the control signals;
- a thresholding circuit having an input connected to the processor output, the thresholding circuit converting the modified communication signal to supply “1” bits and “0” bits at an output,
- a forward error correction (FEC) decoder having an input connected to the thresholding circuit output, the FEC decoder using the forward error correction sections of the modified communication signal for corrections, and supplying a FEC decoder error signal at an output;
- and
- a control unit having a first input connected to the FEC decoder output, the control unit having an output connected to the second input of the processor to supply control signals that are responsive to the FEC decoder error signals;
- wherein the control unit accepts the FEC decoder error signal and compares the number of “1” bits corrected to the number of “0” bits corrected, the control unit modifying the control signal in response to the comparison of “1” bit and “0” bit corrections.
Dependencies are inferred from the claim text.