Method and apparatus for displaying triggered waveform on an error performance analyzer

#The present invention relates to error performance analyzers. This application for patent is a continuation-in-part of Ser. No. 09/723,821 an application filed on Nov. 28, 2000, titled “Method And Apparatus For Displaying Triggered Waveform On An Error Performance Analyzer”, Attorney Docket No. 10003986-1. More specifically, the present invention relates to the method and apparatus for displaying waveforms of binary digit transmission using error performance analyzers.

#A fundamental measure of quality of digital circuits, switches, and transmission systems is the probability of any stored or transmitted bit being transmitted in error, or bit error ratio (BER). The BER is typically tested using a bit error ratio tester (BERT) which may include of a pattern generator and an error detector. The pattern generator and the error detector are often combined in a single unit though this is not required. They are, in fact, sometimes separate units. The pattern generator generates a known sequence of bits (sequence of zeros and ones) for transmission through a device under test (DUT). Typically, the known sequence of bits is often generated by a pseudo-random bit sequencer (PRBS) and is of known length of 2N−1 bits where N may be any number. Commonly, numbers seven (7) or a ten (10) are used as the value of N. The known sequence of bits may be referred to as a base bit sequence, or a base bit pattern. The base bit pattern is continually repeated by the pattern generator.

#The repeated base bit pattern is transmitted to the DUT which, in turn, transmits the bit sequences to be received by the error detector. The error detector compares the received bit sequence with the known bit sequence for error bit detection. Usually, the error detector also generates the known sequence of bits, or repeated base bit pattern, such that the error detector can compare the received bit sequence with the known bit sequence to detect errors in transmission. An error bit is a bit that is sent to the DUT as a zero but transmitted by the DUT as a one, or a bit that is sent to the DUT as a one but transmitted by the DUT as a zero. Then, the number of error bits is compared with the number of bits received. The ratio of the error bits to the sent bits is the bit error ratio, BER. With modern devices, the BER tends to be very low and can be on the order of 10−12 or even less.

#FIG. 1 illustrates a bit error rate testing configuration in simplified blocks;

#FIG. 2 illustrates a sample base bit pattern;

#FIG. 3 illustrates a waveform diagram;

#As shown in the drawings for purposes of illustration, the present invention is embodied in a technique and an apparatus for displaying waveforms using an error performance analyzer. A first bit sequence comprising repeated base bit pattern, each bit either a 0-bit signified by a first bit voltage, VLB, or a 1-bit signified by a second bit voltage, VHB, is received. Then, at a first time within the base bit pattern and each incremental time thereafter for a predetermined period of time, multivalue voltage, VM, is determined. Finally, the multivalue voltage at the first time and the multivalue voltage at each incremental time thereafter is displayed.

#Bit Error Rate Testing Configuration

#Referring to FIG. 1, a basic bit error rate testing configuration is illustrated, in a simplified manner, including a pattern generator 100, a device under test (DUT) 102, an error detector 104, and an oscilloscope 140. The pattern generator 100 sends a repeating sequence of a base bit pattern 101 to the DUT 102 for testing. The base bit pattern 101 is often generated by a pseudo-random bit sequencer (PRBS) 108. Alternatively, the base bit sequence for testing the DUT 102 is stored in memory 110. The pattern generator 100 has a clock 112 to synchronize its operations including the PRBS generation and transmission 101 of the base bit patterns to the DUT 102. The pattern generator 100 may also include a pattern trigger signal generator 134 that may signal 135 at a fixed point in the base bit pattern as it is repeated, for example, at the beginning of the base bit pattern. The pattern trigger need not, and generally does not repeat every repetition of the pattern. But whenever it occurs, it is at the same position in the pattern.