Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port
AssigneeAgilent Technologies, Inc.
InventorJeff Rearick
Life of this patent
Estimating the term…
Abstract
A test method and apparatus allows simultaneous loading of multiple scan chains via a single common scan-in port (SDI) and a scan clock signal SCAN CLOCK. Data is scanned into one or more scanpaths from a scan data in (SDI) port under the control of a clock signal, either directly or indirectly through a linear feedback shift register (LFSR). Scan-out data output from the scanpaths may be read at the scan data out (SDO) port, either directly or indirectly through a signature register with optional masking functionality.
Claims17
A test apparatus for testing a digital circuit comprising:
- a scan data in (SDI) port for serially receiving input scan data;
- a first linear feedback shift register which is operable to receive and shift said input scan data to produce a serial stream of pseudorandom scan data in response to only a test clock signal;
- a scan-in selector which couples one of said input scan data or said serial stream of pseudorandom scan data to serially load a plurality of scanpaths, each of which produces a respective scan-out signal;
- a multiple input signature register coupled to receive said respective scan-out signals and to generate a respective signature corresponding to a function of said respective scan-out signals;
- a scan data out (SDO) port;
- and
- an output selector which couples one of said scan-out signals or said signature to said SDO port.
A method for allowing testing of an integrated circuit, said integrated circuit comprising a scan data in (SDI) port for serially receiving input scan data, a first linear feedback shift register which is operable to receive and shift said input scan data to produce a serial stream of pseudorandom scan data in response to only a test clock signal, a scan-in selector which couples one of said input scan data or said serial stream of pseudorandom scan data to serially load a plurality of scanpaths, each of which produces a respective scan-out signal, a multiple input signature register coupled to receive said respective scan-out signals and to generate a respective signature corresponding to a function of said respective scan-out signals, a scan data out (SDO) port, and an output selector which couples one of said scan-out signals or said signature to said SDO port, said method comprising:
- programming said scan-in selector to couple one or the other of said input scan data and said serial stream of pseudorandom scan data to said plurality of scanpaths;
- and
- programming said output selector to couple one of said scan-out signals or said signature to said SDO port.
Dependencies are inferred from the claim text.