Mult-mode I/O interface for synchronizing selected control patterns into control clock domain to obtain interface control signals to be transmitted to I/O buffers

A multi-mode I/O interface, comprising:

• a transmit state machine receives a core clock signal, a control clock signal and a transmit signal to generate a state signal indicating a state of the I/O interface in a next clock-cycle;
• a pattern generator including one or more pattern generation units to select, in response to the state signal and an I/O protocol signal, one or more N-bit control patterns from a plurality of N-bit control patterns, contained in the one or more pattern generation units;
• a serialization unit to serialize the one or more N-bit control patterns selected by the one or more pattern generation units;
• and
• a synchronization unit to receive the one or more N-bit control patters from the serialization unit and synchronize the control patterns into a control clock domain to form one or more interface control signals generated by the multi-mode I/O interface and transmit the one or more interface control patterns to I/O buffers to enable transmission and receipt of data in accordance with an I/O protocol indicated by the I/O protocol signal.

A system comprising:

• a front side bus for coupling one or more processors to a memory controller hub;
• a memory interface for coupling one or more memories to the memory controller hub;
• one or more I/O ports for coupling one or more peripheral components to the memory controller hub;
• and
• a multi-mode I/O interface for enabling transmission and receipt of data by the memory controller hub including:
• a transmit state machine receives a core clock signal, a control clock signal and a transmit signal and generates a state signal indicating a state of the I/O interface in a next clock-cycle;
• a pattern generator including one or more pattern generation units to select, in response to the state signal and an I/O protocol signal, one or more N-bit control patterns from a plurality of N-bit control patterns, contained in the one or more pattern generation;
• a serialization unit to serialize the one or more N-bit control patterns selected by the one or more patent generation units;
• and
• a synchronization unit receives the one or more N-bit control patters from the serialization unit and synchronizes the control patterns into a control clock domain to form units one or more interface control signals generated by the multi-mode I/O interface and transmit the control patterns to I/O buffers to enable transmission and receipt of data in accordance with an I/O protocol indicated by the I/O protocol signal.