System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation
AssigneeIntel Corporation
InventorSandip Kundu
Life of this patent
Estimating the term…
Abstract
A computer processor includes a plurality of storage elements, such as logic gates and flip-flops, that are interconnected in a first configuration during normal operation of the processor. A plurality of selector elements connected to the storage elements are used to rearrange the storage elements into a second configuration upon entry into a low-power mode of operation. In general, the storage elements, when rearranged into the second configuration, form a chain through which data passes serially for storage in a storage device, such as a memory device or a hard drive.
Claims23
A computer processor system having:
- a plurality of memory storage elements;
- and
- interconnection elements, responsive to detecting which of normal operation or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation by the processor.
A method for use in a computer system having a processor, the method comprising:
- arranging a plurality of memory storage elements in the processor into a first configuration during normal operation of the processor;
- and
- rearranging the memory storage elements into a second configuration upon entering a low-power mode of operation of the processor.
A method comprising:
- restoring power to a processor;
- arranging a plurality of memory storage elements in the processor into a first configuration in which the memory storage elements form a chain;
- loading data from a storage device into a first memory storage element in the chain;
- and
- passing the data through the chain.
A computer system comprising:
- a processor having a plurality of memory storage elements;
- and interconnection elements, responsive to detecting which of normal or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation of the processor and
- a storage device coupled to exchange data with the processor;
- a power supply connected to supply power to the processor during the normal operation and to withhold power from the processor during the low-power mode of operation.
Dependencies are inferred from the claim text.