Reducing power consumption by estimating engine load and reducing engine clock speed
AssigneeATI International SRL
InventorAndrej Zdravkovic
Life of this patent
Estimating the term…
Abstract
A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A number of instructions in the queue is measured. The optimum clock rate is selected based on in part the determined number of queued instructions.
Claims10
A method for reducing power consumption of at least one processor in a system, the processor is associated with at least one queue for storing instructions for execution by the processor, the method comprising:
- analyzing instructions stored in the queue;
- determining a load estimation based on in part a result of the analyzing;
- selecting a clock rate out of a plurality of clocking rates based on in part the determined load estimation;
- and
- clocking the processor at the selected clock rate.
A system having means for reducing power consumption of at least one processor, the processor is associated with at least two queues for storing instructions for execution by the processor, the system comprising:
- means for queuing instructions at a first instruction queue;
- means for distributing instructions queued at said first instruction queue to a second instruction queue where said processor executes the queued instruction from;
- means for analyzing instructions stored in the queues;
- means for determining a load estimation based on in part a result of the analyzing;
- means for selecting a clock rate out of a plurality of clocking rates based on in part the determined load estimation;
- and
- means for clocking the processor at the selected clock rate.
Dependencies are inferred from the claim text.