Method and apparatus for performing sequential executions of elements in cooperation with a transform

A method comprising:

• providing at least three elements, including a first element and a last element, each element having an associated parameter;
• providing a first identifier for the first element;
• for a first sequential execution of the at least three elements, performing a first operation on the first identifier and at least one of the parameters to produce a transform;
• saving the transform;
• and
• for a second sequential execution of the elements, performing a second operation on the transform to produce a last identifier associated with the last element, wherein performing the second operation includes
• shifting the first identifier to produce a shifted identifier, wherein shifting the first identifier includes shifting the first identifier to the left relative to the transform by a number of bits equal in value to one less than a quantity of the at least three elements, and
• performing an exclusive OR operation on the shifted identifier and the transform to produce the last identifier.

A circuit, comprising:

• first and second exclusive OR circuits;
• a first register having an output coupled to a first input of the first exclusive OR circuit and having an input coupled to an output of the first exclusive OR circuit;
• a second register having an output coupled to a first input of the second exclusive OR circuit and having an input;
• a multiplexer having an output coupled to the input of the second register, having a first input coupled to the output of the first exclusive OR circuit, and having a second input coupled to the output of the second register;
• wherein the output of the first exclusive OR circuit is coupled to a second input of the second exclusive OR circuit.

A computer system, comprising:

• an instruction execution pipeline;
• and
• a branch prediction circuit coupled to the instruction execution pipeline and including:
• first and second exclusive OR circuits;
• a first register having an output coupled to a first input of the first exclusive OR circuit and having an input coupled to an output of the first exclusive OR circuit;
• a second register having an output coupled to a first input of the second exclusive OR circuit and having an input;
• and
• a multiplexer having an output coupled to the input of the second register, having a first input coupled to the output of the first exclusive OR circuit, and having a second input coupled to the output of the second register;
• wherein the output of the first exclusive OR circuit is coupled to a second input of the second exclusive OR circuit.

A circuit, comprising:

• a register;
• a data shifting circuit having an input coupled to an output of the register;
• an exclusive OR circuit having a first input coupled to an output of the data shifting circuit;
• an array coupled to a second input of the exclusive OR circuit to transfer transform data to the exclusive OR circuit, and further coupled to the data shifting circuit to transfer data shift information to the data shifting circuit;
• a prediction logic circuit coupled to an output of the exclusive OR circuit;
• and
• a multiplexer having
• an output coupled to an input of the register,
• a first input to receive initial data, and
• a second input coupled to the output of the exclusive OR circuit.

A computer system comprising:

• an instruction execution pipeline;
• a transform generation circuit coupled to the instruction execution pipeline and including:
• a register;
• a data shifting circuit having an input coupled to an output of the register;
• an exclusive OR circuit having a first input coupled to an output of the data shifting circuit;
• an array coupled to a second input of the exclusive OR circuit to transfer transform data to the exclusive OR circuit, and further coupled to the data shifting circuit to transfer data shift information to the data shifting circuit;
• and
• a prediction logic circuit coupled to an output of the exclusive OR circuit;
• and
• a multiplexer having
• an output coupled to an input of the register,
• a first input to receive initial data, and
• a second input coupled to the output of the exclusive OR circuit.

A machine-readable medium having stored thereon instructions, which when executed by at least one processor cause said at least one processor to perform:

• providing at least three elements, including a first element and a last element, each element having an associated parameter;
• providing a first identifier for the first element;
• for a first sequential execution of the at least three elements, performing a first operation on the first identifier and at least one of the parameters to produce a transform;
• saving the transform;
• for a second sequential execution of the elements, performing a second operation on the transform to produce a last identifier associated with the last element;
• using the last identifier to access a location in a prediction array;
• and
• using a content of said location to predict a decision status of the last element, wherein performing the first operation includes:
• performing a first logic function on the first identifier and the parameter associated with the first element to produce a next identifier for a next one of the elements;
• repeating the performing a first logic function on the next identifier and the parameter associated with the next one of the elements, until a last identifier has been produced that is associated with the last element;
• and
• performing a second logic function on the first identifier and the last identifier to produce the transform.