Processor and method for performing a hardware test during instruction execution in a normal mode

A processor, comprising:

• instruction sequencing logic that provides a stream of instructions including a test initiation instruction for execution;
• execution circuitry;
• data storage coupled to said execution circuitry;
• test circuitry that, during execution of said stream of instructions by said execution circuitry in a normal mode of operation, detects for a hardware error in one of said instruction sequencing logic, said execution circuitry, and said data storage in response to said test initiation instruction;
• wherein at least one of said instruction sequencing logic, said execution circuitry, and said data storage includes first circuitry and second circuitry that both perform a same function in response to said test initiation instruction;
• wherein said test circuitry detects for a hardware error by comparing values output in response to said test initiation instruction by said first circuitry and said second circuitry;
• and
• wherein said first circuitry and said second circuitry are each capable of performing at least a first computational function and a different second computational function, said test initiation instruction comprises a first test instruction, and said stream of instructions includes a second test instruction, wherein said first and second circuitry both perform said first computational function in response to said first test instruction and both perform said second computational function in response to said second test instruction.