Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data

A method for processing instructions of a computer program, comprising the steps of:

• providing a pipeline and a scoreboard, said scoreboard including a plurality of multi-bit registers;
• processing one of said instructions via said pipeline;
• detecting that data produced via execution of said one instruction is unavailable;
• detecting a pending instruction for reading said data;
• updating one of said multi-bit registers based on each of said detecting steps;
• retrieving said data in response to said one instruction;
• and
• indicating, via said one multi-bit register, how far said retrieving step has progressed.

A method for processing instructions of a computer program, comprising the steps of:

• providing a pipeline and a scoreboard, said scoreboard including a plurality of multi-bit registers;
• processing one of said instructions via said pipeline;
• detecting that data produced via execution of said one instruction is unavailable;
• detecting a pending instruction for reading said data;
• and
• updating one of said multi-bit registers based on each of said detecting steps,
• wherein said updating step is performed such that said one multi-bit register indicates whether a pending write associated with said one instruction exists and whether said one instruction may be canceled.

A method for processing instructions of a computer program, comprising the steps of:

• providing at least one pipeline and a scoreboard, said scoreboard including at least one multi-bit register;
• processing at least one instruction via said one pipeline;
• identifying a register based on a register identifier defined by said one instruction;
• detecting whether data produced via execution of said one instruction has been written to said register identified in said identifying step;
• retiring said one instruction;
• transmitting said register identifier to said scoreboard in response to a detection in said detecting step that said data produced via execution of said one instruction has yet to be written to said register identified in said identifying step;
• changing a first bit in said one multi-bit register based on said register identifier transmitted in said transmitting step;
• controlling, subsequent to said retiring step, said one multi-bit register such that said one multi-bit register is indicative of whether said one instruction may be canceled;
• and
• determining, based on said controlling step, whether to cancel said one instruction.

A system for processing instructions of a computer program, comprising:

• a plurality of pipelines configured to process and execute said instructions;
• and
• a scoreboard coupled to said pipelines, said scoreboard indicative of which of a plurality of registers are associated with pending writes induced by retired instructions, said scoreboard comprising data indicative of which of said retired instructions may be canceled,
• wherein said data indicates which portions of a memory hierarchy have been searched in response to one of said retired instructions.

A system for processing instructions of a computer program, comprising:

• a plurality of pipelines configured to process and execute said instructions;
• and
• a scoreboard coupled to said pipelines, said scoreboard indicative of which of a plurality of registers are associated with pending writes induced by retired instructions, said scoreboard comprising data indicative of which of said retired instructions may be canceled, wherein a portion of said data is stored in a multi-bit register of said scoreboard, said data portion indicative of whether one of said plurality of registers is associated with a pending write induced by one of said retired instructions,
• wherein said data portion indicates which portions of a memory hierarchy have been searched in response to said one retired instruction.

A method for processing instructions of a computer program, comprising the steps of:

• providing a pipeline and a scoreboard, said scoreboard including a plurality of multi-bit registers;
• processing one of said instructions via said pipeline;
• retrieving data in response to said one instruction;
• writing said retrieved data to a register identified by a register identifier defined by said one instruction;
• detecting that said data has yet to be written to said identified register;
• determining how far through a memory hierarchy said retrieving step has progressed;
• and
• updating, prior to said writing step, one of said multi-bit registers based on said detecting step and said determining step.