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US 6,715,049 B1Granted
Microcomputer and information processing system
AssigneeKabushiki Kaisha Toshiba
InventorYoshiki Hayakashi
Life of this patent
Estimating the term…
Abstract
A microcomputer and an information processing system protect data stored therein and secure the safety of the data. The microcomputer (1) has a memory (3), a read protect register (13), and a write protect register (14). The protect registers store addresses that represent protected areas in the memory where an access from the outside is prohibited. If an access from the outside involves an address of the protected areas, the access to the memory is disabled.
Claims15
A computer comprising:
- a memory having at least one port shared by an external device and an internal device and having a protected area where an access from the external device is prohibited;
- a CPU configured to control a bus right for access to address and data buses running between the CPU and the memory by devices internal and external to said computer;
- and
- a control circuit, comprising a read-protect register and a write-protect register configured to hold a protected address corresponding to the protected area in the memory, and configured to compare the protected address with a target address of an external device memory read or write access and to disable said external device memory read or write access if the target address corresponds to the protected address.
1 more element
A computer comprising:
- a CPU;
- a memory accessible from the CPU and a device external to said computer via a common port and including a read-protected area which is protected from being accessed by the external device;
- an address bus configured to transfer an address from one of the CPU and the external device;
- a data bus configured to transfer data between the memory and one of the CPU and the external device;
- a signal line configured to transfer a read control signal from one of the CPU and the external device when reading data from the memory;
- a signal line configured to transfer a write control signal from one of the CPU and the external device when writing data to the memory;
- an input/output buffer configured to control data input/output between the data bus and the external device in response to an output enable signal;
- an address decoder configured to enable the memory upon receiving an address from the address bus;
- a gate configured to set the memory to a write enabled state in response to the write control signal and a write enable signal;
- an output control circuit including a read-protect register and configured to generate the output enable signal and supply the output enable signal to the input/output buffer;
- and
- a write control circuit including a write-protect resister and configured to generate the write enable signal and supply the write enable signal to the gate.
9 more elements
A computer comprising:
- a CPU;
- a memory accessible from the CPU and a device external to said computer via a common port and including a read-protected area which is protected from being accessed by the external device;
- an address bus configured to transfer an address from one of the CPU and the external device;
- a data bus configured to transfer data between the memory and one of the CPU and the external device;
- a signal line configured to transfer a read control signal from one of the CPU and the external device to the memory when reading data from the memory;
- an input/output buffer configured to control data input/output between the data bus and the external in response to an output enable signal;
- and
- an output control circuit including a read-protect register and configured to generate the output enable signal and supply the output enable signal to the input/output buffer to protect the read-protected area of the memory from being accessed by the external device.
5 more elements
A computer comprising:
- a CPU;
- a memory accessible from the CPU and a device external to said computer via a common port and including a read-protected area which is protected from being accessed by the external device;
- an address bus configured to transfer an address from one of the CPU and the external device;
- a data bus configured to transfer data between the memory and one of the CPU and the external device;
- a signal line configured to transfer a write control signal from one of the CPU and the external device to the memory when writing data to the memory;
- a gate configured to set the memory to a write enabled state according to an AND of the write control signal and a write enable signal;
- and
- a write control circuit having a write-control register and configured to generate the write enable signal and supply the write enable signal to the gate to restrict access to protect the read-protected area of the memory from being accessed by the external device.
5 more elements
An information processing system comprising:
- a microcomputer having a memory accessible by an external device;
- a CPU configured to control a bus right that authorizes the use of address and data buses running between the CPU and the memory by receiving a bus right request from the external device and, if the request is acceptable, providing the external device with the bus right to a common port;
- a register, comprising at least one of a read-protect resister and a write-protect register, and configured to hold a protected address that represents a protected area in the memory where an access from the external device is prohibited;
- a control circuit configured to compare the protected address with a target address of a read or write access made from the external device to the memory after the bus right is given to the external device, and if the target address is within the protected addresses, disabling the read or write access;
- and
- an external bus master unit configured to issue the bus right request to the CPU, receive a bus right authorization from the CPU if the request is accepted by the CPU, and access the memory through the address and data buses according to the bus right authorization.
3 more elements
A microcomputer comprising:
- an address bus having an external terminal;
- a data bus having an external terminal;
- a control bus having an external terminal;
- a bus right request signal line having an external terminal;
- a bus right authorization signal line having an external terminal;
- a CPU connected to the address bus, data bus, and control bus, said CPU configured to release a bus right after accepting a bus right request from an external device;
- a memory connected to the CPU and an external device through the address bus, the data bus, and the control buss where a write access to the memory is enabled in response to a write enable signal;
- means for storing data specifying a protected area in the memory where an access is prohibited;
- and
- a controller configured to monitor an address in the address bus while a bus right authorization signal is active in a bus right authorization signal line and prohibiting an access to the memory if the access is made to the protected area of the memory in response to the bus right request from the external device.
7 more elements
Dependencies are inferred from the claim text.