Efficient memory management mechanism for digital signal processor and method of operation thereof

Abstract

For use in a processor having an instruction cache, an instruction memory and an external synchronous memory, a memory management mechanism, a method of managing memory and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes an external memory request abort circuit coupled to the external synchronous memory and an instruction cache invalidator associated with the external memory request abort circuit. In this embodiment, the external memory request abort circuit aborts a request to load an instruction from the external synchronous memory before the information is loaded into the instruction cache. Additionally, the instruction cache invalidator invalidates the instruction cache when address spaces of the instruction memory and the external synchronous memory overlap and the processor switches between the instruction memory and the external synchronous memory.

Dependencies are inferred from the claim text.