Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency

A method of processing data in a computer system having a plurality of processors and a cache coupled to the plurality of processors, the method comprising the steps of:

• a) generating a request to process a portion of data;
• b) pointing to a portion of the cache containing the portion of data;
• c) associating a plurality of tag entries with the plurality of processors, each tag entry comprising a pointer;
• d) associating a plurality of data entries with the plurality of processors, wherein each of the plurality of data entries comprises an owner bit for each of the plurality of processors, wherein the owner bit indicates that a corresponding processor is currently accessing the cache;
• and
• e) determining if the pointer of one of the plurality of tag entries associated with the plurality of processors points to a data entry comprising the portion of data, wherein no data entries are stored in the plurality of tag entries.

A processing system comprising:

• a plurality of processors;
• a memory controller coupled to the plurality of processors, the memory controller including a cache, the cache comprising:
• a tag array comprising a plurality of tag entries, wherein each of the plurality of tag entries comprises a tag and a pointer;
• a data array comprising a plurality of data entries, wherein each of the plurality of data entries comprises an owner bit for each of the plurality of processors, wherein the owner bit indicates that a corresponding processor is currently accessing the cache, wherein each pointer points to one of the plurality of data entries, wherein no data entries are stored in the tag array.