US 6,715,025 B2 · Information processing apparatus using index and tag addresses for cache

Abstract

In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

Claims19

Dependent claims

An information processing apparatus comprising:

a central processing unit;
an address mapping circuit receiving a first address and a write back address to form bank addresses and a row/column address;
a DRAM memory having a plurality of banks;
first and second address buses for transferring said bank addresses from said address mapping circuit to said DRAM memory;
and
a data bus for transferring read and write data;
wherein read operation to one of said banks and write back operation to another one of said banks has an overlapping period.

4 more elements

Dependencies are inferred from the claim text.

Information processing apparatus using index and tag addresses for cache

Life of this patent

Information processing apparatus using index and tag addresses for cache

Life of this patent

Abstract

Claims19