Synchronous integrated circuit device

An integrated circuit device comprising:

• a plurality of output drivers to output block size information to a second integrated circuit device, wherein the block size information represents an amount of data to be output by the second integrated circuit device;
• a delay locked loop to generate an internal clock signal;
• and
• a plurality of input receivers, coupled to the delay locked loop, to sample the amount of data output by the second integrated circuit device, wherein the amount of data is sampled synchronously with respect to the internal clock signal.

An integrated circuit device for controlling a synchronous memory device, the integrated circuit device comprises:

• clock receiver circuitry to receive an external clock signal;
• delay locked loop circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal;
• and
• a first plurality of output drivers, coupled to the delay locked loop circuitry, to output an amount of write data synchronously with respect to the internal clock signal.

An integrated circuit controller device for controlling a synchronous dynamic random access memory device, the controller device comprises:

• a first plurality of output drivers to output block size information to the memory device, wherein the block size information represents an amount of data to be output by the memory device;
• a second plurality of output drivers to output an operation code to the memory device, wherein the operation code specifies a read operation, and wherein the memory device outputs the amount of data to the controller device in response to the operation code;
• and
• a plurality of input receivers to receive the amount of data output by the memory device.