PCI/PCI-X bus bridge with performance monitor

Abstract

A bus bridge for use in a data processing system is disclosed in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus. The bridge may monitor events such as accepting a posted memory write (PMW), accepting with split response a read request (RR), retrying a PMW, retrying a RR, disconnecting a PMW when the bridge is a target of the operation, and accepting a PMW, accepting a split read completion operation (SRC), accepting a RR with split response, accepting a split write request operation (SWR) with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, and disconnecting a SRC when the bridge is a master. In a PCI-X to PCI-X embodiment of the bridge, the bridge may monitor the primary, and secondary busses are PCI-X or PCI busses and the events monitored including accepting a PMW, accepting a SRC, accepting a RR with spilt response, accepting a SWR with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is a target and accepting a PMW, accepting a SRC, accepting a RR with split response, accepting a SWR with split response, accepting a RR with immediate response, accepting a SWR with immediate response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is a master. In either embodiment, the bridge may further include a mode register corresponding to each performance monitor register where the value of the mode register determines the specified activity monitored by the corresponding performance monitor register.

Dependencies are inferred from the claim text.