Method and system for reducing latency in message passing systems
AssigneeInternational Business Machines Corporation
InventorsJorge R. Rodriguez, Shailabh Nagar
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Abstract
A method and system for synchronizing message transfers from a sender to a receiver, such that message latency and overhead processing are minimized. A next inter-message arrival delay is initially predicted in accordance with traffic history. The predicted inter-message arrival delay is categorized as either an intra-burst delay or an inter-burst delay. In response to a prediction of an inter-burst delay, the receiver is operated in a blocking mode wherein the receiver waits for an interrupt request from the sender. In response to a prediction of an intra-burst delay, the receiver is switched to a polling mode wherein the receiver polls for a message complete signal from said sender.
Claims21
A method for synchronizing message transfers from a sender to a receiver, said method comprising:
- determining a present level of message traffic from a sender to a receiver by modeling said present traffic level utilizing a bimodal sequencer that sequences between burst periods and non-burst periods, such that said present level of message traffic is determinable as one of at least three traffic levels including a burst, a non-burst, and a transition to or from a burst;
- predicting an inter-message arrival delay based on said determined present level of message traffic;
- in response to predicting that said inter-message arrival delay is an inter-burst delay, operating said receiver in a blocking mode such that said receiver waits for an interrupt request from said sender;
- and
- in response to predicting that said inter-message arrival delay is an intra-burst delay, operating said receiver in a polling mode such that said receiver polls for a message complete signal from said sender.
An apparatus for synchronizing message transfers from a sender to a receiver, said apparatus comprising:
- processing means for determining a present level of message traffic from a sender to a receiver, wherein said processing means further comprises processing means for modeling said present traffic level utilizing a bimodal sequencer that sequences between burst periods and non-burst periods, such that said present level of message traffic is determinable as one of at least three traffic levels including a burst, a non-burst, and a transition to or from a burst;
- processing means for predicting an inter-message arrival delay based on said determined present level of message traffic;
- processing means responsive to predicting that said inter-message arrival delay is an inter-burst delay, for operating said receiver in a blocking mode such that said receiver waits for an interrupt request from said sender;
- and
- processing means responsive to predicting that said inter-message arrival delay is an intra-burst delay, for operating said receiver in a polling mode such that said receiver polls for a message complete signal from said sender.
A program product within a computer readable storage media for synchronizing message-transfers from a sender to a receiver, said program product comprising:
- instruction means for determining a present level of message traffic from a sender to a receiver, wherein said instruction means further comprises instruction means for modeling said present traffic level utilizing a bimodal sequencer that sequences between burst periods and non-burst periods, such that said present level of message traffic is determinable as one of at least three traffic levels including a burst, a non-burst, and a transition to or from a burst;
- instruction means for predicting an inter-message arrival delay based on said determined present level of message traffic;
- instruction means responsive to predicting that said inter-message arrival delay is an inter-burst delay, for operating said receiver in a blocking mode such that said receiver waits for an interrupt request from said sender;
- and
- instruction means responsive to predicting that said inter-message arrival delay is an intra-burst delay, for operating said receiver in a polling mode such that said receiver polls for a message complete signal from said sender.
Dependencies are inferred from the claim text.