Method and means for enhanced interpretive instruction execution for a new integrated communications adapter using a queued direct input-output device
AssigneeInternational Business Machines Corporation
InventorsFrank W. Brice, Jr., Janet R. Easton, Steven Messinger, Richard P. Tarcza, Leslie W. Wyman
Life of this patent
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Abstract
Method and means to provide a mechanism by which a hypervisor can permit a real machine to interpretively execute certain I/O instructions independently of the value of an I-bit in the subchannel. This is necessary as the I-bit covers all I/O instructions that can be interpretively executed; however, there can be instances where the hypervisor cannot allow the interpretive execution of other I/O instructions but can permit the interpretive execution of the SIGA instruction.
Claims10
In a network computing system having a main storage capable of connecting to at least one application server and an interface element with at least one adapter and a plurality of subchannels, said system being capable of establishing processing communication with at least one application user(s), a method providing an enhanced interpretive instruction execution comprising the steps of:
- determining if a second level of interpretive execution is needed by assessing whether said computing system contains one or more logically partitioned environments;
- determining if a second level of interpretive execution is needed by assessing whether said computing system contains an hypervisor environment created within another hypervisor environment;
- creating an I-bit in said subchannels for controlling all I/O instructions and allowing said bit to indicate which I/O instructions are to be interpretively executed when said second level is not present;
- creating a new bit within the interpretive-execution state description;
- defining a mechanism designed for controlling all second level execution;
- said mechanism signalling that interception of all I/O instructions has to be made when said second level is not present, when both the I-bit for the applicable subchannel and said new bit in said system are set to zero;
- said mechanism prohibiting interception and allowing for interpretive execution of commands when either the I-bit or said new bit has a value of one;
- in case a second level of interpretive instruction execution is detected, said mechanism allowing interception to occur when either said new bit in second-level state description is zero, or when both said I-bit for applicable subchannel and said new bit are zero;
- in case a second level of interpretive instruction execution is detected, said mechanism prohibiting interception but allowing for interpretive execution of commands when said new bit in said second-level state description is one and either the I-bit for the subchannel or said new bit contains a value of one.
In a network computing system having a main storage capable of connecting to at least one application server and an interface element with at least one adapter and a plurality of subchannels, said system being capable of establishing processing communication with at least one application user(s), an apparatus for providing an enhanced interpretive instruction execution comprising the steps of:
- an analyzer for determining if a second level of interpretive execution is needed by assessing whether said computing system contains one or more logically partitioned environments;
- said analyzer also determining if a second level of interpretive execution is needed by assessing whether said computing system contains an hypervisor environment created within another hypervisor environment;
- an I-bit created in said subchannels to control all I/O instructions and allowing said bit to indicate which I/O instructions are to be interpretively executed when said second level is not present;
- a new bit created within the interpretive-execution state description;
- a mechanism designed for controlling all second level execution;
- said mechanism signalling that interception of all I/O instructions has to be made when said second level is not present, when both the I-bit for the applicable subchannel and said new bit in said system are set to zero;
- said new mechanism prohibiting interception but allowing for interpretive execution of commands when either the I-bit or said new bit has a value of one;
- in case a second level of interpretive instruction execution is detected, said mechanism allowing interception to occur when either said new bit in a second-level state description is zero, or when both said I-bit for the applicable subchannel and said new bit are zero;
- in case a second level of interpretive instruction execution is detected, said mechanism prohibiting interception but allowing for interpretive execution of commands when said new bit in said second-level state description is one and either the I-bit for the subchannel or said new bit contains a value of one.
Dependencies are inferred from the claim text.