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AssigneeNational Semiconductor Corporation
InventorJeffrey A. Lohman
Estimating the term…
There is disclosed a denormal handling circuit for use in a pipelined floating point unit containing an addition pipe and/or a multiplication pipe. The denormal result handling circuit comprises a denormal condition detection circuit associated with at the addition pipe and/or the multiplication pipe for examining a first operand and a second operand loaded into the addition pipe and/or the multiplication pipe and detecting a potential denormal condition. The denormal condition indicates that a calculated result generated from the first and second operands may be a denormal result. The denormal condition detection circuit, in response to detection of a potential denormal condition, prevents an additional operation from being loaded into the addition pipe and/or the multiplication pipe. The denormal result handling circuit also comprises a complex rounding unit for receiving the calculated result from the addition pipe and/or the multiplication pipe and, in response to the detection of the potential denormal condition, rounding the calculated result.
For use in a pipelined floating point unit comprising at least one of an addition pipe and a multiplication pipe, a denormal result handling circuit comprising:
A processor comprising:
For use in a pipelined floating point unit comprising at least one of an addition pipe and a multiplication pipe, a method of handling a denormal result comprising the steps of:
Dependencies are inferred from the claim text.