Hardware accelerator for normal least-mean-square algorithm-based coefficient adaptation

Abstract

A system and method for accelerating least-mean-square algorithm-based coefficient adaptation which executes in one machine clock cycle one tap of the least-mean-square algorithm including data fetch, coefficient fetch, coefficient adaptation, convolution, and write-back of a new coefficient vector. A data memory stores an input signal. A coefficient memory stores a coefficient vector. A multiplication and accumulation unit reads the input signal from the data memory and the coefficient vector from the coefficient memory to perform convolution. A coefficient adaptation unit separate from the multiplication and accumulation unit reads the input signal from the data memory and reads the coefficient vector from the coefficient memory to perform coefficient adaptation at the same time that the multiplication and accumulation unit performs the reading to produce an adapted coefficient vector which is written back into the coefficient memory for use by the multiplication and accumulation unit during a next iteration of convolution to produce an output signal, wherein each tap is executed in one machine clock cycle.

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