High speed random number generation

A mechanism for generating random numbers on demand, having a physical random number generator (5), having a data input and an output, and a pseudo-random generator (6) coupled to the output of the physical random generator (5), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator (5) comprising a logic circuit (10) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H1 and the clock input (CLK) adapted to receive a second “low frequency” clock signal H2, the “high frequency” signal H1 adapted to be sampled by the “low frequency” signal H2, the two clock signals H1 and H2 being of different frequencies respectively and issuing from two different first (OSC1) and second (OSC2) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit (10), the logic circuit (10) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit (1.0) being accentuated by phase noise of the first oscillator (OSC1) generating the “high frequency” signal H1, the pseudo-random generator (6) being arranged to re-inject part of the pseudo-random output signal into the physical generator (5) and an internal memory (9) for storing random numbers obtained as output signals from the pseudo-random generator (6) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator (5) and the pseudo-random number generator (6) running on the same second “high frequency” clock signal H generated by the external oscillator (7), comprising a random number generator (1) and further including a dual-port memory (3) including a receiving buffer (31), coupled to the output of the generator (1) via a bus, and a microprocessor (2) coupled to the dual-port memory (3) via a microprocessor bus, communicating with the generator (1) via the dual-port memory (3) and posting in the dual-port memory (3) a command word comprising an address and a count containing a maximum number of random words to be stored, and the receiving buffer (31) of the dual-port memory (3), at the request of the microprocessor (2), arranged to be fed by the internal memory (9) of the generator (1) until a count corresponding to a given maximum number of random numbers has elapsed, then utilized by the microprocessor (2).

A card for accelerating the cryptographic functions of a computing machine, characterized in that it supports a random generator (1) comprising a physical random number generator (5), having a data input and an output, and a pseudo-random generator (6) coupled to the output of the physical random generator (5), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator (5) comprising a logic circuit (10) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H1 and the clock input (CLK) adapted to receive a second “low frequency” clock signal H2, the “high frequency” signal H1 adapted to be sampled by the “low frequency” signal H2, the two clock signals H1 and H2 being of different frequencies, respectively, and issuing from two different first (OSC1) and second (OSC2) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit (10), the logic circuit (10) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit (1.0) being accentuated by phase noise of the first oscillator (OSC1) generating the “high frequency” signal H1, the pseudo-random generator (6) being arranged to re-inject part of the pseudo-random output signal into the physical generator (5) and an internal memory (9) for storing random numbers obtained as output signals from the pseudo-random generator (6) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator (5) and the pseudo-random number generator (6) running on the same second “high frequency” clock signal H generated by the external oscillator (7).

A card for accelerating the cryptographic functions of a computing machine, characterized in that it supports a mechanism for generating random numbers on demand, having a physical random number generator (5), having a data input and an output, and a pseudo-random generator (6) coupled to the output of the physical random generator (5), said pseudo-random generator having an input adapted to receive a germ delivered by the physical generator and an output from which is delivered a pseudo-random output signal, said physical generator (5) comprising a logic circuit (10) having a set up time and at least a data input (D) and a clock input (CLK), the data input (D) adapted to receive a first “high frequency” clock signal H1 and the clock input (CLK) adapted to receive a second “low frequency” clock signal H2, the “high frequency” signal H1 adapted to be sampled by the “low frequency” signal H2, the two clock signals H1 and H2 being of different frequencies, respectively, and issuing from two different first (OSC1) and second (OSC2) oscillators operating asynchronously from one another and not adhering to the setup time of the logic circuit (10), the logic circuit (10) arranged to deliver at an output thereof a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence, the metastability of the signal obtained as an output from the logic circuit (1.0) being accentuated by phase noise of the first oscillator (OSC1) generating the “high frequency” signal H1, the pseudo-random generator (6) being arranged to re-inject part of the pseudo-random output signal into the physical generator (5) and an internal memory (9) for storing random numbers obtained as output signals from the pseudo-random generator (6) and an external oscillator having a “high frequency” clock signal output (H), the physical random number generator (5) and the pseudo-random number generator (6) running on the same second “high frequency” clock signal H generated by the external oscillator (7), comprising a random number generator (1) and further including a dual-port memory (3) including a receiving buffer (31), coupled to the output of the generator (1) via a bus, and a microprocessor (2) coupled to the dual-port memory (3) via a microprocessor bus, communicating with the generator (1) via the dual-port memory (3) and posting in the dual-port memory (3) a command word comprising an address and a count containing a maximum number of random words to be stored, and the receiving buffer (31) of the dual-port memory (3), at the request of the microprocessor (2), arranged to be fed by the internal memory (9) of the generator (1) until a count corresponding to a given maximum number of random numbers has elapsed, then utilized by the microprocessor (2).