Image processing device having matrix computing units
AssigneeSega Enterprises, Ltd.
InventorYusuke Shimizu
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AssigneeSega Enterprises, Ltd.
InventorYusuke Shimizu
Estimating the term…
A geometry processor 10 has an image processing device having a matrix computing unit 14 that is connected to a vector bus VB through which coordinate conversion target data is supplied and a matrix bus MB through which coordinate conversion matrix is supplied, and that performs multiplication of the coordinate conversion target data by the coordinate conversion matrix, wherein the processor is provided with a switching unit 24 that supplies a mixture ratio S28 to the vector bus VB and interpolation computation target data S18 to the matrix bus MB, and wherein the matrix computing unit 14 performs interpolation computation of the interpolation computation target data S18 in accordance with the mixture ratio S28. According to this invention, the interpolation computation needed for a subdivision surface process and other processes may be performed using the matrix computing unit 14 provided in the geometry processor, normally for the purpose of coordinate conversion. Therefore, it is not necessary to incorporate a dedicated interpolation computing unit in the geometry processor, and the circuit size of the geometry processor may be reduced. Furthermore, the vector product computation may be performed using the matrix computing unit 14.
An image processing device comprising:
An image processing device comprising:
A program product for causing a image processing device having a matrix computing unit to perform a coordinate conversion process, interpolation computation process or vector product computation process, said matrix computing unit being connected to a vector bus through which first matrix data is supplied as well as to a matrix bus through which second matrix data is supplied, and performing multiplication of said first and second matrix data, comprising the steps of:
A program product for causing a image processing device having a matrix computing unit to perform a subdivision surface process, said matrix computing unit being connected to a vector bus through which first matrix data is supplied as well as to a matrix bus through which second matrix data is supplied, and performing multiplication of said first and second matrix data, to perform a subdivision surface process,
Dependencies are inferred from the claim text.