Method and device for synchronization of phase mismatch in communication systems employing a common clock period

A method of receiving a data signal in a communication system wherein both transmitter and receiver employ a common clock period, comprising:

• a first acquiring step of acquiring the data signal on respective first active edges of a clock signal;
• detecting a presence of metastability relative to said respective first active edges and said data signal;
• a second acquiring step of acquiring said data signal on respective second active edges of said clock signal;
• and
• synchronizing said data signal acquired on said respective second active edges with said first active edges.

A transceiver, comprising:

• means for transmitting data according to a clock signal having a period;
• means for receiving data, including:
• first means for acquiring data on respective first active edges of a clock signal having said period;
• means for detecting a presence of metastability relative to said respective first active edges and said data;
• second means for acquiring said data on respective second active edges of said clock signal;
• means for synchronizing said data acquired on said respective second active edges with said first active edges;
• and
• means for outputting said data acquired on said respective first active edges when metastability is not detected and outputting said synchronized data when metastability is detected.

A device to overcome a metastable state in a communication system employing a common clock period, comprising:

• a first latch and a second latch, the first latch being clocked by a clock signal and the second latch being clocked by an inverted version of said clock signal, each of the first and second latches receiving a data stream;
• a delay device, the delay device delaying an output of the second latch by one half of a cycle of said clock signal;
• and
• a multiplexer, said multiplexer outputting an output of said first latch when said received data stream does not exhibit metastability relative to said clock signal outputting an output of said delay device in a presence of metastability, and further including a sequence recognizer, sequence recognizer being configured to recognize a predetermined bit sequence on said output of said first latch and to control said multiplexer to output said output of said delay device upon failing to detect said predetermined bit sequence.

A transceiver, comprising:

• circuitry for transmitting data according to a clock signal having a period;
• circuitry for receiving data, including:
• first circuitry for acquiring data on respective first active edges of a clock signal having said period;
• circuitry for detecting a presence of metastability relative to said respective first active edges and said data;
• second circuitry for acquiring said data on respective second active edges of said clock signal;
• circuitry for synchronizing said data acquired on said respective second active edges with said first active edges;
• and
• circuitry for outputting said data acquired on said respective first active edges when metastability is not detected and outputting said synchronized data when metastability is detected.