Integrated services digital broadcasting deinterleaver architecture
AssigneeLSI Logic Corporation
InventorsCheng Qian, Advait Mogre
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Abstract
An apparatus comprising a memory, a write pointer, a read pointer and a control circuit. The memory may have a plurality of memory locations accessed by a plurality of addresses. The write pointer may be configured to write data to the memory in response to a sequence of write addresses generated in response to a first control signal. The read pointer may be configured to read data from the memory in response to a sequence of read addresses generated in response to a second control signal. The control circuit may be configured to generate (i) the first control signal, and (ii) the second control signal. The order data is read from said memory may comprise a de-interleaved pattern with respect to the order the data is written to the memory.
Claims20
An apparatus comprising:
- a memory having a plurality of memory locations accessed by a plurality of addresses;
- a write pointer configured to write data to said memory in response to a sequence of write addresses generated in response to a first control signal;
- a read pointer configured to read data from said memory in response to a sequence of read addresses generated in response to a second control signal;
- and
- a control circuit configured to generate (i) said first control signal, and (ii) said second control signal, wherein the order said data is read from said memory comprises a de-interleaved pattern with respect to the order said data is written to said memory.
An apparatus comprising:
- means for storing data in a plurality of memory locations accessed by a plurality of addresses;
- means for writing data to said memory locations in response to a sequence of write addresses generated in response to a first control signal;
- means for reading data from said memory locations in response to a sequence of read addresses generated in response to a second control signal;
- and
- means for generating (i) said first control signal, and (ii) said second control signal, wherein the order said data is read from said memory locations comprises a de-interleaved pattern with respect to the order said data is written to said memory locations.
A method for de-interleaving integrated services digital broadcast super frames comprising the steps of:
- (A) writing data to a memory in response to a sequence of write addresses generated in response to a first control signal;
- (B) reading data from said memory in response to a sequence of read addresses generated in response to a second control signal;
- and
- (C) generating (i) said first control signal, and (ii) said second control signal, wherein the order data is read from said memory comprises a de-interleaved pattern with respect to the order said data is written to said memory.
Dependencies are inferred from the claim text.