Method and apparatus for efficient processing of signal in a communication system

In a communication system, a RAM structure comprising:

• a block of RAM partitioned into two sets of blocks of RAM, wherein each set includes a plurality of blocks of RAM;
• a write pointer for writing data symbols into a first set of said two sets of blocks of RAM, wherein said writing is according to a predefined interleaving function;
• a read pointer for sequentially reading data symbols from a second set of said two sets of blocks of RAM;
• wherein each block of said plurality of blocks of RAM includes at least two sub-blocks of RAM;
• wherein, via said write pointer, one of said least two sub-blocks of RAM stores in-phase data symbols, and another quad-phase data symbols.

In a communication system, a method comprising:

• partitioning a RAM structure into a plurality of blocks of RAM;
• partitioning each of said plurality of blocks of RAM into two sets of blocks of RAM, wherein each set includes a plurality of blocks of RAM;
• writing, for each of said plurality of blocks of RAM, data symbols into a first set of said two sets of blocks of RAM, wherein said writing is according to a predefined interleaving function;
• sequentially reading, for each of said plurality of blocks of RAM, data symbols from a second set of said two sets of blocks of RAM;
• for each of said plurality of blocks of RAM, partitioning each block of said plurality of blocks of RAM to at least two sub-blocks of RAM;
• wherein, for each of said plurality of blocks of RAM, via said writing step, one of said least two sub-blocks of RAM stores in-phase data symbols, and another quad-phase data symbol.

In a communication system, an apparatus comprising:

• a RAM structure partitioned into a plurality of blocks of RAM, wherein each of said plurality of blocks of RAM partitioned into two sets of blocks of RAM, wherein each set includes a plurality of blocks of RAM;
• write pointer for each of said plurality of blocks of RAM for writing data symbols into a first set of said two sets of blocks of RAM, wherein said writing is according to a predefined interleaving function;
• read pointer for each of said plurality of blocks of RAM for sequentially reading data symbols from a second set of said two sets of blocks of RAM;
• wherein, for each of said plurality of blocks of RAM, each block of said plurality of blocks of RAM includes at least two sub-blocks of RAM;
• wherein, for each of said plurality of blocks of RAM, via said write pointer, one of said least two sub-blocks of RAM stores in-phase data symbols, and another quad-phase data symbols.