Semiconductor memory and control method

Abstract

The present invention provides a semiconductor memory device and control method capable of effectively suppressing the generation of operating current originating in noise of address signals provided from the outside without impairing the operating speed during reading and writing. This semiconductor memory device is provided with a filter circuit (102) for removing noise contained in address signals provided from the outside, a circuit system containing an ATD circuit (311) for generating a first address transition detection signal (φATD1) by detecting a change in an address signal prior to passing through the filter circuit (102), and a circuit system containing an ATD circuit (321) for generating a second address transition detection signal (φATD2) by detecting a change in an address signal after passing through the filter circuit (102). Refresh operation is controlled by first address transition detection signal (φATD1), while read/write operation is controlled by second address transition detection signal (φATD2). As a result, only the refresh operation is performed in the case noise has been generated, and the generation of operating current is effectively suppressed.

Dependencies are inferred from the claim text.