Semiconductor memory device having divided word line structure

A semiconductor memory device, comprising:

• a plurality of memory cells arranged in rows and columns, and divided into a plurality of blocks long a column direction;
• a plurality of global word lines each arranged in common to said plurality of blocks, at every K (K:
• natural number) memory cell rows;
• a plurality of word lines separately arranged for each of said memory rows, in correspondence to said plurality of blocks respectively;
• a global decoder setting a voltage of said plurality of global word lines in accordance with a result of row selection;
• a plurality of local decoder selection circuits provided in correspondence to said plurality of blocks respectively, each generating K selection signals associated with respective K word lines associated with each of said global word lines, in accordance with selection information of said plurality of blocks and said result of row selection;
• K selection signal lines provided for each of said blocks, to transmit, respectively, said K selection signals from a corresponding one of said plurality of local decoder selection circuits;
• a plurality of local decoders provided in correspondence to said plurality of word lines respectively, each controlling activation of a corresponding one of said word lines in accordance with a voltage of a corresponding one of said K selection signal lines and a voltage of a corresponding one of said plurality of global word lines,
• each of said local decoders including
• a first switch circuit connecting, in accordance with a voltage of a first node connected to one of the corresponding selection signal line and a corresponding one of said global word lines, a second node connected to the other one of the corresponding selection signal line and the corresponding global word line with an internal node,
• a driver circuit to set said corresponding word line in an activated state when said internal node is set at a first voltage via said first switch circuit, and to set said corresponding word line in an inactivated state when said internal node is set at a second voltage, and
• a second switch circuit to connect said internal node with said second voltage;
• and
• a control circuit to turn off said second switch circuit, in another operation mode different from a normal operation mode, where multiple ones of said plurality of word lines are simultaneously activated, in said local decoder corresponding to each of the simultaneously-activated plurality of word lines.