Memory array with dual wordline operation

A memory array system comprising;

• a plurality of memory cells arranged in an array having a plurality of wordlines traversing the plurality of memory cells;
• a memory controller having means for accessing an address directory register storing an address and a status of each of the plurality of memory cells, said memory controller further having means for determining the address and status of at least one of the plurality of memory cells and means for activating a single wordline or at least two wordlines during a data array accessing cycle;
• and
• means for interchanging cells between a single-cell array and a twin-cell array mode of operation of at least one of the plurality of memory cells.

Wordline decoding circuitry for controlling wordline activation for a memory array having a plurality of memory cells, said wordline decoding circuitry comprising:

• circuitry for receiving at least one control signal;
• wordline activation circuitry for enabling single wordline activation or dual wordline activation according to said received at least one control signal;
• and
• circuitry for interchanging between a single-cell and a twin-cell array mode of operation of at least one memory cell.