Method and architecture for refreshing a 1T memory proportional to temperature

An apparatus for controlling a refresh of a memory array comprising:

• means for monitoring a charge leakage of an array of memory cells;
• means for monitoring a discharge leakage of an array of memory cells;
• and
• means for generating a refresh control signal in response to either a voltage level of said first monitoring means rising above a first pre-determined threshold level or a voltage level of said second monitoring means dropping below a second pre-determined threshold level, wherein said first and second threshold levels are different.

A method for controlling a refresh operation of a memory array comprising the steps of:

• monitoring a charge leakage of a first monitor cell;
• monitoring a discharge leakage of a second monitor cell;
• and
• generating a refresh control signal in response to either a voltage level of said first monitor cell rising above a first pre-determined threshold level or a voltage level of said second monitor cell dropping below a second pre-determined threshold level, wherein said first and second pre-determined threshold levels are different.