On-chip compression of charge distribution data
AssigneesAgilent Technologies, Inc., Texas Instruments Incorporated
InventorsJuergen T. Rickes, Hugh P. McAdams
Life of this patent
Estimating the term…
Abstract
A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One embodiment includes a compression circuit coupled to sense amplifiers. Each sense amplifier compares a series of reference voltages to a corresponding bit line and sets a result value for the comparison. A series of result values from a sense amplifier has a transition when the bit line voltage is approximately equal to the reference voltage. The compression circuit can use the transition as a trigger to record a compressed value indicating the reference voltage at the transition.
Claims19
A method for testing an integrated circuit containing memory cells, comprising:
- (a) reading out a signal from one of the memory cells to a bit line;
- (b) biasing a reference line to a first/next voltage from a series of voltages;
- (c) generating a result signal indicating whether the first/next voltage on the reference line is higher than a voltage on the bit line;
- (d) repeating steps (b) and (c) for each of the voltages in the series to thereby generate a series of values of the result signal;
- and
- (e) compressing the series of values signals using on-chip circuitry to generated a compressed measurement value.
An integrated circuit comprising:
- an array of memory cells including bit lines coupled to respective columns of the memory cells;
- a reference voltage generator operable in a test mode to generate a reference signal that sequentially has a series of voltages;
- sense amplifiers connected to the bit lines and the reference voltage generator;
- and
- an on-chip compression circuit coupled to receive output signals from the sense amplifiers, wherein the on-chip compression circuit is operable to compress a series of values of one of the output signals from the sense amplifiers to generate a compressed value.
A compression circuit for test data generated in a memory, comprising:
- a counter that changes a count value to correspond to a reference voltage supplied to a sense amplifier;
- and
- a storage element coupled to receive the count value and a result signal indicating a result of a sensing operation during which the sense amplifier compares a bit line voltage to the reference voltage, wherein
- in response to the result signal having a first value, the storage element sets a stored value equal to the count value;
- and
- in response to the result signal having a second value, the storage element leaves the stored value unchanged.
Dependencies are inferred from the claim text.