Semiconductor memory device having reduced chip select output time
AssigneeSamsung Electronics Co., Ltd.
InventorsGong-Heum Han, Choong-Keun Kwak, Kyeong-Yoon Bae
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Abstract
A semiconductor memory device is provided to generate a series of pulse signals in response to the activation of an internal chip select signal from an internal chip select buffer when an external chip select signal transitions from an inactive state to an active state. With this configuration, a chip select output time (tco) is more reduced as compared to prior arts. Further, the chip select output time is reduced to be equal to an address access time (tAA) because a designer can control the chip select output time. As a result, the whole access time of the semiconductor memory device can be reduced.
Claims20
A semiconductor memory device for inputting/outputting data in response to an external chip select signal and an address signal that are inputted through signal input terminals, the semiconductor memory device comprising:
- a memory cell array for storing data;
- a write/read circuit for writing/reading the data to/from the memory cell array;
- a first input circuit for transferring the address signal to the write/read circuit through the signal input terminal in response to a first control signal;
- and
- a control logic circuit for detecting whether the address signal inputted to the first input circuit transitions, and for generating a series of pulse signals so that the write/read circuit writes/reads a data signal,
- wherein the control logic circuit generates the series of pulse signals in response to the activation of an internal chip select signal from the first input circuit when the external chip select signal transitions from inactive to active, wherein the control logic circuit comprises:
- a second input circuit for receiving the external chip select signal and activating the first control signal and a second control signal when the external chip select signal is active;
- a detect circuit for detecting whether the address signal inputted to the first input circuit transitions while the second control signal is activated, and outputting an address transition detect signal;
- a pulse enable control circuit for activating a pulse enable signal in response to the address transition detect signal when the first control signal is active, and for activating the pulse enable signal when the first control signal transitions from an inactive state to an active state;
- and
- a pulse generation circuit for generating the series of the pulse signals in response to the pulse enable signal.
A semiconductor memory device for inputting/outputting data in response to an external chip select signal and an address signal that are inputted through signal input terminals, the semiconductor memory device comprising:
- a memory cell array for storing data;
- a write/read circuit for writing/reading the data to/from the memory cell array;
- a first input circuit for transferring the address signal inputted through the signal input terminal to the write/read circuit in response to a first control signal;
- and
- a control logic circuit for detecting whether the address signal inputted to the first input circuit transitions to generate a series of pulse signals so that the write/read circuit writes/reads a data signal,
- wherein the control logic circuit comprises:
- a second input circuit for receiving the external chip select signal and outputting the first control signal and a second control signal in response to the external chip select signal;
- a short pulse generation circuit for generating a short pulse signal when the address signal inputted to the first input circuit transitions;
- and
- pulse generating means for generating a series of pulse signals when the second control signal is active and the short pulse signal is inputted from the short pulse generation circuit, and for generating the series of the pulse signals when the second control signal transitions from an inactive state to an active state.
A method for inputting/outputting data in response to an externals chip select signal and an address signal that are inputted through signal input terminal of a semiconductor memory device, the method comprising the steps of:
- storing data;
- writing/reading the data to/from a memory cell array;
- transferring the address signal inputted through a signal input terminal to a write/read circuit in response to a first control signal;
- and
- detecting whether the address signal inputted to a first input circuit transitions to generate a series of pulse signals so that the write/read circuit writes/reads a data signal.
Dependencies are inferred from the claim text.